|
|
Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIA |
Post Reply 
|
| Author | |
Olaf.MuellerAE 
Active User 
Joined: 27 Feb 2015 Status: Offline Points: 28 |
 Post Options
 Thanks(0)
 Quote Reply
 Topic: Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIAPosted: 10 Feb 2021 at 2:04am |
|
Hello all,
Can someone explain me the difference between PROHIBIT_VIA and PROHIBIT_VIA_HOLE? These keep-out layers come up during eCADSTAR export. For me each PROHIBIT_VIA is also a PROHIBIT_VIA_HOLE. I see no sense for a single PROHIBIT_VIA_HOLE area. Best Regards, Olaf
|
|
 |
|
|
|
|
Tom H
Admin Group 
Joined: 05 Jan 2012 Location: San Diego, CA Status: Offline Points: 5716 |
Post Options
Thanks(0)
Quote Reply
Posted: 12 Feb 2021 at 9:01am |
|
I have the following definitions for you: - Via Keepout: prevents a via being placed on that layer. - Via Hole Keepout: allows a via to be stop on that layer, but prevents it passing through the dielectric layer below that layer. As Via Hole Keepout prevents a via from going through the dielectric layer below it, it is not valid for the bottom layer due to having no dielectric layer below. This function was not available in the older CADSTAR. Best regards / Mit freundlichen Grüßen Karl-Heinz Kluwetasch Geschäftsführender Gesellschafter | Chief Executive Officer |
|
|
|
|
Post Reply
|
|
| Tweet |
| Forum Jump | Forum Permissions You cannot post new topics in this forum You cannot reply to topics in this forum You cannot delete your posts in this forum You cannot edit your posts in this forum You cannot create polls in this forum You cannot vote in polls in this forum |
Topic Options