Print Page | Close Window

Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIA

Printed From: PCB Libraries Forum
Category: PCB Footprint Expert
Forum Name: Questions & Answers
Forum Description: issues and technical support
URL: https://www.PCBLibraries.com/forum/forum_posts.asp?TID=2815
Printed Date: 07 Oct 2024 at 1:23am


Topic: Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIA
Posted By: Olaf.MuellerAE
Subject: Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIA
Date Posted: 10 Feb 2021 at 2:04am
Hello all,

Can someone explain me the difference between PROHIBIT_VIA and PROHIBIT_VIA_HOLE?

These keep-out layers come up during eCADSTAR export.

For me each PROHIBIT_VIA is also a PROHIBIT_VIA_HOLE. I see no sense for a single PROHIBIT_VIA_HOLE area.

Best Regards,
Olaf


Replies:
Posted By: Tom H
Date Posted: 12 Feb 2021 at 9:01am
I have the following definitions for you:

- Via Keepout: prevents a via being placed on that layer.
- Via Hole Keepout: allows a via to be stop on that layer, but prevents it passing through the dielectric layer below that layer.

As Via Hole Keepout prevents a via from going through the dielectric layer below it, it is not valid for the bottom layer due to having no dielectric layer below.

This function was not available in the older CADSTAR.

Best regards / Mit freundlichen Grüßen
 
Karl-Heinz Kluwetasch
Geschäftsführender Gesellschafter  |  Chief Executive Officer



-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Print Page | Close Window