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Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIA |
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Olaf.MuellerAE 
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Joined: 27 Feb 2015 Status: Offline Points: 28 |
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 Topic: Difference PROHIBIT_VIA_HOLE and PROHIBIT_VIAPosted: 10 Feb 2021 at 2:04am |
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Hello all,
Can someone explain me the difference between PROHIBIT_VIA and PROHIBIT_VIA_HOLE? These keep-out layers come up during eCADSTAR export. For me each PROHIBIT_VIA is also a PROHIBIT_VIA_HOLE. I see no sense for a single PROHIBIT_VIA_HOLE area. Best Regards, Olaf
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Tom H
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Joined: 05 Jan 2012 Location: San Diego, CA Status: Offline Points: 5718 |
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Posted: 12 Feb 2021 at 9:01am |
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I have the following definitions for you: - Via Keepout: prevents a via being placed on that layer. - Via Hole Keepout: allows a via to be stop on that layer, but prevents it passing through the dielectric layer below that layer. As Via Hole Keepout prevents a via from going through the dielectric layer below it, it is not valid for the bottom layer due to having no dielectric layer below. This function was not available in the older CADSTAR. Best regards / Mit freundlichen Grüßen Karl-Heinz Kluwetasch Geschäftsführender Gesellschafter | Chief Executive Officer |
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