Solder Joint Goals - Take II

Message Topic Search Topic Options Post Reply Create New Topic Printable Version Translate Topic

   Tom,

Below are some quotes snipped from your prior thread titled "New 2016 Solder Joint Goals" (any misrepresentation due to improper snipping is unintentional):

 Tom H wrote:

<In IPC-7351B,> All Chip components have a 0.35 mm Toe with 0.00 mm Side and Heel regardless if they are a 0201 or 1206. In reality, each chip size requires its own unique solder joint goals.

 Tom H wrote:

The chip height was ruled out primarily because of multiple component sources required for each part number.

Using Height to determine a land pattern will be popular in the future because it nails down a perfect pattern for a specific package.

Using Height to determine a land pattern would dramatically increase the number of different patterns in everyone's CAD library and the industry is not ready for that yet.

 Tom H wrote:

Various heights in an 0805 Capacitor have no impact on the land pattern. One pattern can be sufficient for all 0805 Capacitors. 

The IPC-J-STD-001 standard for solder joint acceptability states that the Maximum Toe value for every electronic package should not exceed 0.50 mm. If if does exceed 0.50 mm then the solder will simply melt on the pad rather than forming a fillet up the side of the terminal lead. 

The IPC-J-STD-001 indicates that the Toe solder joint should be a minimum of 25% of the terminal lead height.

I'm reading what appears to be conflicting thoughts on what matters (perhaps only in terms of what PCB LE generates?).  First you say each component requires unique solder goals (you may have been speaking in terms of different component styles, but that's probably semantics).  Then you say component height was ruled out as an input as every manufacturer does their own thing (so swapping components is complicated).  Then you say using height is bound to be popular, but it will complicate libraries due to the large number of unique footprints (no argument here to either point).  Finally, you say one pattern is sufficient for all 0805 caps, regardless of height.

But then it gets interesting.  You specifically point out J-STD's requirements for Toe having a minimum height of 25% of the package (or lead) height, and a maximum of 0.50mm.

So, I wanted to understand how PCB LE reacted to varying heights on "popcorn" components.  I selected the common 0402 resistor and had it create a number of footprints in varying heights.  I was surprised to see every single one had a Toe of 0.17mm, regardless of height... that will work okay up to ~0.70mm in component height, but beyond that the Toe should get longer (it doesn't).  Can you provide an explanation as to why the Toe does not appear to be tied to the component height?  Is that by design, based upon your earlier thread's comment about height not mattering, and if so, how to resolve the conflict between that explanation and J-STD guidelines?

Of course, beyond 2.00mm in component height, the Toe should stop growing, but I doubt we'll see many 0402 components that high (though some readily exist up to nearly 0.90mm).

Thanks!