Tom,

Below are some quotes snipped from your prior thread titled "New 2016 Solder Joint Goals" (any misrepresentation due to improper snipping is unintentional):

Tom H wrote: <In IPC-7351B,> All Chip components have a 0.35 mm Toe with 0.00 mm Side and Heel regardless if they are a 0201 or 1206. In reality, each chip size requires its own unique solder joint goals.

Tom H wrote: The chip height was ruled out primarily because of multiple component sources required for each part number. Using Height to determine a land pattern will be popular in the future because it nails down a perfect pattern for a specific package. Using Height to determine a land pattern would dramatically increase the number of different patterns in everyone's CAD library and the industry is not ready for that yet.

Tom H wrote: Various heights in an 0805 Capacitor have no impact on the land pattern. One pattern can be sufficient for all 0805 Capacitors. The IPC-J-STD-001 standard for solder joint acceptability states that the Maximum Toe value for every electronic package should not exceed 0.50 mm. If if does exceed 0.50 mm then the solder will simply melt on the pad rather than forming a fillet up the side of the terminal lead. The IPC-J-STD-001 indicates that the Toe solder joint should be a minimum of 25% of the terminal lead height.

I'm reading what appears to be conflicting thoughts on what matters (perhaps only in terms of what PCB LE generates?).  First you say each component requires unique solder goals (you may have been speaking in terms of different component styles, but that's probably semantics).  Then you say component height was ruled out as an input as every manufacturer does their own thing (so swapping components is complicated).  Then you say using height is bound to be popular, but it will complicate libraries due to the large number of unique footprints (no argument here to either point).  Finally, you say one pattern is sufficient for all 0805 caps, regardless of height.

But then it gets interesting.  You specifically point out J-STD's requirements for Toe having a minimum height of 25% of the package (or lead) height, and a maximum of 0.50mm.

So, I wanted to understand how PCB LE reacted to varying heights on "popcorn" components.  I selected the common 0402 resistor and had it create a number of footprints in varying heights.  I was surprised to see every single one had a Toe of 0.17mm, regardless of height... that will work okay up to ~0.70mm in component height, but beyond that the Toe should get longer (it doesn't).  Can you provide an explanation as to why the Toe does not appear to be tied to the component height?  Is that by design, based upon your earlier thread's comment about height not mattering, and if so, how to resolve the conflict between that explanation and J-STD guidelines?

Of course, beyond 2.00mm in component height, the Toe should stop growing, but I doubt we'll see many 0402 components that high (though some readily exist up to nearly 0.90mm).

Thanks!

In the case of the 0402 Chip package, IPC-J-STD-001 indicates the Toe goal should be 25% of the Height or 0.50 mm, whichever is Less. 

The vast majority of 0402 Chip Capacitor height is 0.65 mm or less. Only Murata makes a 0402 capacitor higher. The average 0402 Capacitor height is 0.55 mm and 0402 Resistor height is 0.40 mm. 

We're also using the IPC-7351 3-Tier land pattern system for pad size calculation. The 7351 specification only has one Toe value for each Terminal Lead and it's not based on Height. So when combining IPC-7351 and IPC-J-STD-001 we had to break up the Terminal Leads into package sizes using the above average height and everything below. 

The Chip package height cannot be the primary factor in establishing the Toe solder joint goal. You must take the worst case scenario and work backwards to figure out a single Toe goal for a specific package size. Otherwise your PCB library would be littered with various footprints for the same package size. 

Our customers want to use the same 0402 footprint for all of their 0402 packages and that is the challenge we had to overcome by evaluating worst case scenarios but eliminating the couple of packages that are out of range. 

Footprint Expert uses the IPC-7351 mathematical model for pad size and location calculations. But we also use IPC-J-STD-001 rules for solder joint goal acceptability. 

If your package height falls out of range of the standard package heights, you can select the "Footprint" tab and enter the mfr. recommended pattern, or select the Terminal tab and adjust the Toe goal to fit your concern. Either way, every value of Footprint Expert calculator is editable by the end user. You have the control to create whatever Toe value you need for your component packages.