Print Page | Close Window

IPC-7351 Padstack Naming Convention

Printed From: PCB Libraries Forum
Category: Libraries
Forum Name: PCB Library Construction Guidelines
Forum Description:
URL: https://www.PCBLibraries.com/forum/forum_posts.asp?TID=36
Printed Date: 21 Nov 2024 at 11:59pm


Topic: IPC-7351 Padstack Naming Convention
Posted By: Nick B
Subject: IPC-7351 Padstack Naming Convention
Date Posted: 31 Mar 2012 at 5:46am

INTRODUCTION

 

The padstack consists of combinations of letters and numbers that represent shape, or dimensions of lands on different layers of printed boards or documentation. The name of the padstack needs to represent all the various combinations. These are used in combination with the land pattern conventions defined herein according to the rules established in the IPC-2220 Design standards.

 

The first part of the padstack convention consists of a land shape. There are six basic land shape identifiers. Note: All alphabetical characters are “lower case”. This helps discriminate numeric values.

 

Basic Land Shape Letters

 

c = Circular   

s = Square

r = Rectangle

b = Oblong

u = User Defined Contour (Irregular Shape)

d = D Shape (Square on one end and Circular on the other end)

 

Padstack Defaults

 

  • Solder Mask is 1:1 scale of the land size
  • Paste Mask is 1:1 scale of the land size
  • The Assembly Layer land is 1:1 scale of the land size
  • Inner Layer Land is the same shape as the outer layer land
  • The Primary and Secondary lands are the same size
  • The inner layer land shapes are Circular
  • Vias are Circular
  • Thermal ID, OD and Spoke Width sizes follow the IPC Level A, B or C
  • Plane Clearance Anti-pad size follows the IPC Level A, B or C
  • Thermals have 4 spokes
  • Mounting Holes are Circular

Note: Every board fabricator’s ability to register solder mask is different.  The 1:1 scale solder mask covers the variation, and so long as manufacturers are building to specs such as IPC-6012 that say you can’t have mis-registration of the solder mask. 

           

Illegal characters that cannot be used (Microsoft requirement) include “ ” , ; : / \ [ ] ( ) . { } * & % # $ ! @ ^ =

 

Examples utilizing the padstack naming convention (all values are in metric units)

Note: Every number goes two places to the right and as many as needed to the left of the decimal

Examples: 1150 = 11.50 mm or 11500 μm, 150 = 1.50 mm or 1500 μm, 15 = 0.15 mm or 150 μm

 

c150h90 where “c” denotes a Circular land with a 1.50 diameter and H denotes a hole size of 0.90

c130_95 Donut pad where “c” denotes a Circular land with a 1.30 OD diameter and 95 denotes the ID diameter
c130_95hn Donut pad - “c” denotes a Circular land with a 1.30 OD diameter and 95 denotes the ID diameter and hn70 denotes hole, non-plated 0.70 diameter
c130_95hn70k147 Donut pad - “c” denotes a Circular land with a 1.30 OD diameter and 95 denotes the ID diameter and hn70 denotes hole, non-plated 0.70 diameter and k147 denotes a keep-out 1.47 diameter
v50h25 where a “v” denotes a via with a 0.50 land (default Circular land) and H denotes a 0.25 hole

s150h90 where “s” denotes a 1.50 Square land and H denotes a hole size of 0.90

s350 where ‘s” denotes a square SMT land size of 3.50

r200_100 where “r” denotes a Rectangular SMT land 2.00 land length X 1.00 land width

b300_150 where “b” denotes a SMT Oblong land size of 3.00 X 1.50

b400_200h100 where “b” denotes an Oblong land size of 4.00 length X 2.00 width and 1.00 hole

d300_150 where “d” denotes land with one circular end and one square end (looks like a D) 3.00 X 1.50

v30h15l1-3 where “v” denotes a 0.30 blind via with 0.15 Hole; 1 is the starting layer, 3 is the end layer

r200_100r5 = Rounded Rectangular 2mm X 1mm X 0.05mm radius corners

r200_100c10 = Chamfered Rectangular 2mm X 1mm X 0.1mm chamfered corners

v30h15l3-6 where “v” denotes a 0.30 buried via with 0.15 Hole; 3 is the starting layer, 6 is the end layer

 

The through hole “IPC-7251 Padstacks.xls” file should be used as the basis for a new chart in IPC-7251 and IPC-7351B.  Note: Draft supporting paragraphs with formula that document the math involved.

It is assumed that the padstack has the same value as the mounted layer size and shape for –

  • Inner Layer
  • Opposite Side
  • Solder Mask
  • Solder Paste
  • Assembly Layers

It is also assumed that the “Plane Clearance” and “Thermal Relief” data follows the through-hole convention guidelines defined in the IPC-2221 and IPC-2222 standards.

 

Modifiers that are used when padstack features are different than the defaults

 

These are the “Variants” or “Modifiers” that go after the basic padstack naming convention.

These are used when the User needs to change the padstack default values either by a different dimension or a different shape. In instances where shapes are different this becomes a two letter code with the modifier first followed by the land shape letter.

 

n = Non-plated Hole

z = Inner Layer land dimension if different than the land on primary layer

x = Special modifier used alone or following other modifiers for lands on opposite side to primary layer land dimension

t­ = Thermal Relief; if different than IPC standard padstack – tid_od_sw for 4 spoke default      

m = Solder Mask if different than default 1:1 scale of land

p = Solder Paste if different than default 1:1 scale of land

a = Assembly surface land if different than default 1:1 scale of land

y = Plane Clearance (Anti-pad) if the value is different than the Thermal OD

o = Offset Land Origin

k = Keep-out

r = Radius for Rounded Rectangular Land Shape

c = Chamfer for Chamfered Rectangular Land Shape

 

Shape change is the last letter in the string prior to the dimension.

 

Other usage of the padstack naming convention

 

USE of letter v: Vias can be named using the padstack naming convention. Because most vias use lands that are circular in shape, the letter V will be used in place of the letter C in the padstack naming convention. If this is not true the modifiers can be added after the letter V to signify shape or dimensional changes to this default.

 

USE of letter w: In addition to Vias the padstack naming convention can also be used for defining mounting holes. The letter W shall be used to define the mounting hole characteristics and any associated lands used for the surface lands (either plated or un-plated)

Examples of double character modifiers:

 

ts = Thermal Square; if different than the top side land shape and dimensions

sw = Thermal spoke width

zs = Inner Layer Land Shape is Square (Note: The default is circular)

m0 = No Solder Mask

mxc = Solder Mask Opposite Side Circular

mx0 = Solder Mask Opposite Side No Solder Mask

xc = Opposite Side Circular

vs = Via with Square land

hn = Non-plated Hole

 

Modifier Example for Through-hole:

 

s150h90zs150 = where “s” is Square 1.50 land with 0.90 Hole with 1.50 inner (Z) Layer Square land

c150h90zc150 = where “c” is Circular 1.50 land with 0.90 Hole with 1.50 inner (Z) Layer Circular land

 

Modifier Examples for Vias:

 

vs50h25 where “vs” denotes a 0.50 Square Via with a 0.25 Hole

v50h25xs70 where “v” is 0.50 Circular Via with 0.25 Hole and 0.70 Square land on opposite side

 

Chamfered & Rounded corner modifiers are used to indicate which corner(s) are modified.

Order of precedence has been given to the first 4 modifiers.

 

Modifiers:
bl – bottom left
br – bottom right
ul – upper left
ur – upper right
ulr – upper left & right

blr – bottom left & right

ubl – upper and bottom left

ubr – upper and bottom right

 

Rounded and Chamfered lands in “one corner” Modifier Examples:

 

r100_200rbl50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in bottom left corner

 

r100_200rbr50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in bottom right corner

 

r100_200rul50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in upper left corner

 

r100_200rur50 = rectangular land 1.00 x 2.00 with 0.50 radius for rounded corner in upper right corner

 

r100_200cbl50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in bottom left corner

 

r100_200cbr50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in bottom right corne

 

r100_200cul50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in upper left corner

 

r100_200cur50 = rectangular land 1.00 x 2.00 with 0.50 chamfer for chamfer corner in upper right corner

Examples of a square land with 3 rounded and 1 chamfered corner (for Thermal Pad)

 

s300p190r25cul50 = square 3.00 land, square paste 1.90, corner radius 0.25, upper-left chamfer 0.50

 

s300p190r25cbl50 = square 3.00 land, square paste 1.90, corner radius 0.25, bottom-left chamfer 0.50

 

 

Chamfered and Rounded Rectangular with all four corners chamfered does not need a corner modifier.

 

Modifier Examples with Rounded Rectangle Land Shape:

 

r200_100r50 = rectangular land 2.00 x 1.00 with 0.50 radius for rounded corners in all 4 corners

r200_100c50 = rectangular land 2.00 x 1.00 with 0.50 chamfer for chamfered corners in all 4 corners

 

Examples of a padstack with Circular land with hole using various modifiers

 

c150h90 = Default padstack with a 1.50 circular land with a 0.90 hole (no modifiers used)

 

c150hn90 = Default padstack with a 1.50 circular land with a 0.90 non-plated hole (no modifiers used)

 

c150h90z140 = Inner layer land is smaller than external lands 1.40 or 0.10 smaller

 

c150h90z140x170 = Opposite side land is larger than top side land 1.70 or 0.20 larger

 

c150h90z140x170m165mx185 = Solder mask opening for top and bottom lands 0.15 larger for each

 

c150h90z140x170m165mX185a200 = Assembly drawing land in 0.50 larger than 1.50 primary land

 

c150h90z140x170m165mx185a200y300 = Plane clearance anti-pad diameter is 3.00

 

c150h90z140x170m165mx85 = Solder mask encroachment on opposite land by 0.65 smaller

 

c150h90m165 = adding a solder mask opening of 1.65 diameter or 0.15 larger than land

 

c150h90t150_180_40 = Thermal ID 1.50, OD 1.80, Spoke Width 0.40, Anti-pad 1.80

 

c150h90t150_180_40y200 = Anti-pad 2.00 (because the size is different than the Thermal OD)

 

c150h90t150_180_80_2 = Spoke Width 0.80 with 2 Spokes

 

c150h90m165t150_180_40 = Solder Mask 1.65

 

 

Examples of a padstack with Oblong land with Slotted Hole

 

Sample – b = Oblong Land Shape then “X” dimension (length) then Underscore _Y” dimension (width)

 

b400_200h300_100 = Oblong land 4mm length X 2mm width with slotted hole size 3mm X 1mm

 

b400_200hn300_100 = Oblong land 4mm X 2mm with non-plated slotted hole size 3mm X 1mm

 

 

Examples of a SMT padstack land using various modifiers

 

b300_150 = Default padstack with a 3.00 length and 1.50 width land (no modifiers used)

 

b300_150m330_180 = Solder Mask is 0.30 larger than the land on all sides

 

b300_150m330_180p240_140 = Solder Paste is smaller by 0.10 width and 0.60 length

 

b300_150b-50 = Oblong Land 3.0mm X 1.5mm w/Offset Origin negative 0.5mm

 

r400_200po430_230 = Rectangle SMT land 4.00 X 2.00 with a Oblong Solder Paste size of 4.30 X 2.30

 

 

Example of Thermal Pads for QFN, SON, QFP and SOP

Square Configurations

 

s480p4s152 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each

 

s480p4s152cul50 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each with 0.50mm Chamfer in Upper Left corner

 

s480p4s152cul50r25 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each with 0.50mm Chamfer in Upper Left corner with 0.25mm corner Radius

Example of a Mounting Hole

 

w700h400z520m720 = This is a Plated Through Mounting hole for a #6-32 screw using a 4.00 diameter hole and having a circular 7.00 land on the primary and secondary side of the board, with a solder mask clearance that is 0.20 larger than the 7.20 land. The internal lands are smaller that the external and are also circular 5.20 in diameter.

 

w700hn400z520m720 = Non-plated version

 

Example of a Local Fiducial for Fine Pitch SMT Components

 

c100m200k200 = Circular Land 1.00 with Solder Mask 2.00 with Keep-out 2.00

s100m200k200 = Square Land 1.00 with Solder Mask 2.00 with Keep-out 2.00

 

Example of Proportional Plated Through-hole padstack

 

c150h100 = 1.5mm circular pad with 1mm hole with 1.5mm solder mask with 1.5mm plane clearance with 1.5mm assembly outline with Thermal Relief w/4 spokes 0.4mm width with ID 1.5mm and OD 1.8mm

 

Example of Proportional Non-plated Through-hole padstack

 

c100hn150 = 1mm circular pad with 1.5mm hole “non-plated” with 1.5mm solder mask with 2.35mm plane clearance with 2.1mm keep-out



-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn



Replies:
Posted By: DaveCowl
Date Posted: 18 Oct 2012 at 4:24pm
I need a circular pad that does not have a paste shape since the part is not soldered down, rather it is a 'compression' fit.

What should the pad be named?

c40p0 ?

Cheers!


Posted By: Tom H
Date Posted: 25 Oct 2012 at 10:50am
That's correct! 0 = No Paste


Posted By: budnoel
Date Posted: 14 Dec 2012 at 7:53am
I thought I saw a rule stating that the padstacks should be rounded up to the nearest .05mm  All of the proportional through-hole PS are in multiples of .05mm


Posted By: Tom H
Date Posted: 14 Dec 2012 at 11:42am
Through-hole padstack technology is currently still in the 0.05 mm resolution while SMT technology has advanced to the 0.01 mm resolution.
 
The primary driver behind SMT high resolution is the introduction of microminiature component packages and component lead terminal sizes.
 
It's difficult to miniaturize through-hole component technology however, when we release the new "Package Editor" in February, the user will have 100% control of customizing padstack generation.
 
So the current 0.05 mm through-hole resolution is compatible with the unreleased IPC-7251 standard but the resolution will shift when non-standard through-hole library solutions become available.
 


Posted By: DaveCowl
Date Posted: 09 May 2013 at 11:06am
Is there a naming convention where the internal layer pad of a via is different from the top layer?

I need one that is v25h10l1-2 but on layer two the pad is '20', not '25'...

Cheers! Dave.


Posted By: Tom H
Date Posted: 09 May 2013 at 12:29pm
Yes, it would be very similar the the Padstack Naming Convention.
 
You're on the right track.
 
Go here to download the Padstack Naming Convention (and many other docs) -
http://www.pcblibraries.com/forum/pcb-library-construction-guidelines_forum30.html" rel="nofollow - http://www.pcblibraries.com/forum/pcb-library-construction-guidelines_forum30.html


Posted By: PLTcbv
Date Posted: 19 Jun 2013 at 1:26am
Hi,
 
How do we create a correct padstack name for a " Pad 2.7 mm with a Hole Rnd 2.0 +Tol 0.1 -Tol 0 mm"
 
So how do we define hole tolerances in padstack names?
 
Regards,
Wim


Posted By: Tom H
Date Posted: 19 Jun 2013 at 6:50am
IPC-7351B introduced the padstack naming convention.
 
There was no consideration to add the "hole tolerance" to the padstack name.
 
You would have to append the padstack name at the end and since there is no standard for how to represent this, you can invent your own.
 
My recommendation would be a double character modifier like "ht" (hole tolerance) and then the range.
 
You don't have to include the units as everything is considered metric (millimeters).
 


Posted By: matthelm
Date Posted: 21 Jun 2013 at 12:25pm
Tom,
A few suggestion for the NEXT spec for padstack naming convention.  (Tom, you've done a great job, these are ONLY suggestions)

1. Use um for the base unit.  This way the spec can go smaller when needed, and you don't need to worry where the decimal point goes, as there isn't any.

2. Support leading zeros.  This is mainly so the names sort correctly for human interaction.  I'm really getting tired of seeing list in 3 different orders, depending on what tool/system is viewing them.  You will hit a few exceptions (I currently use 4 in um and 3 in mils, and I have a few inch based pads (maybe 10) over 3 digits , but I'd rather have that, than all my 10 mil and 100 mil and 11 and 100 mil, etc. pads near each other.

A software converter could handle both of these easy, as all you would be doing is adding a Leading/trailing zero, or this could easily be a switch only used when creating the pad, not in storage.  BTW, for dimensions in part names, I use the same system, but add 1 digit (5 & 4) on each unit.  It works very well for me.  I don't think I've had any parts fall out of the standard names.



Posted By: PLTcbv
Date Posted: 25 Jun 2013 at 12:12am
Tom,

When do we use the"u" for a padstack?
Looking at the document I see: u = User Defined Contour (Irregular Shape)

Some examples in the document:
s300p190r25cul50 = square 3.00 land, square paste 1.90, corner radius 0.25, upper-left chamfer 0.50
u480p4s152cul50 = 4.80mm Square Land with 4 Paste Mask Squares 1.52mm each with 0.50mm Chamfer in Upper Left corner

They are both squares with a upper-left chamfer, so an Irregular Shape.
Why is the first a "s" and the second a "u"?



Posted By: Tom H
Date Posted: 25 Jun 2013 at 7:24am
The letter "u" is used twice.
 
If you see the letter "u" as the very 1st character it represents "user defined pad shape".
 

c = Circular   

s = Square

r = Rectangle

b = Oblong

u = User Defined Contour (Irregular Shape)

d = D Shape (Square on one end and Circular on the other end)

 
If you see "u" in the middle of the padstack name it represents "Upper" when chamfered or radius corners are used.
 

bl – bottom left
br – bottom right
ul – upper left
ur – upper right
ulr – upper left & right

blr – bottom left & right

ubl – upper and bottom left

ubr – upper and bottom right



-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: PLTcbv
Date Posted: 26 Jun 2013 at 1:30am
I understand that the letter "u" is used twice.

I was just wondering when to use a "s" and when a "u".
If you look at s300p190r25cul50 and u480p4s152cul50 in the document these are both a Square land with 0.5 mm Chamfer in Upper Left Corner, but sometimes the padstack starts with "s" and sometimes it starts with "u".


Posted By: Tom H
Date Posted: 26 Jun 2013 at 6:51am
To use "u" for a square pad with a corner chamfer is the wrong application of the IPC padstack naming convention.
 
If the first character is "u" the pad shape is irregular (free form) and not square.
 
Are you telling me that the FP Designer produces a padstack name of u480p4s152cul50?
 


-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: PLTcbv
Date Posted: 26 Jun 2013 at 7:03am
No, I was looking at the begin off this post.
Look at:
Examples of a square land with 3 rounded and 1 chamfered corner (for Thermal Pad)
and
Example of Thermal Pads for QFN, SON, QFP and SOP

Both square pad different notation.


Posted By: Tom H
Date Posted: 26 Jun 2013 at 7:10am
Well then thanks for pointing that out so we can get the record straight.
 
"u" should not be used for the primary letter for square pads with chamfers.
 


-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: PLTcbv
Date Posted: 21 Aug 2013 at 7:06am
Padstack Naming Convention: 
Chamfered & Rounded corner modifiers are used to indicate which corner(s) are modified.

Order of precedence has been given to the first 4 modifiers.

 

Modifiers:
bl – bottom left
br – bottom right
ul – upper left
ur – upper right


If you use the Padstack Designer in PCB LE Lite the modifiers are:

ll - Lower left

lr - Lower right

ul - Upper left

ur - Upper right



Which is correct bl or ll / br or lr?




Posted By: Tom H
Date Posted: 21 Aug 2013 at 7:46am
Once Jeff gets back from vacation in a week, we'll fix this padstack naming convention to match IPC-7351.
 
Thanks for reporting this!
 


-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: Nick B
Date Posted: 01 Sep 2013 at 4:31am
This was fixed in 2013.11, to be released within the next couple days.

-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: PLTcbv
Date Posted: 11 Sep 2013 at 2:06am
I'm looking at 2013.12 and it looks like it was't fixed.

Still "Lower Left" and "Lower Right". Should be according IPC "Bottom Left" and "Bottom Right".


Posted By: PLTcbv
Date Posted: 08 Nov 2013 at 6:28am
I have checked the latest version (2013.16) but the naming for the Chamfer Location is still not fixed.


Still "Lower Left" and "Lower Right". Should be according IPC "Bottom Left" and "Bottom Right".


Posted By: chads108
Date Posted: 20 Mar 2014 at 6:03am
Any suggestions for naming multi-drill padstacks?


Posted By: SteveD
Date Posted: 23 Jun 2015 at 11:41am
What is the terminal layer in a pad stack?  And why do some components have it, and others do not?


Posted By: Matthew Lamkin
Date Posted: 05 Oct 2015 at 2:17am
I have someone asking a question about this.

  • Inner Layer Land is the same shape as the outer layer land
  • The inner layer land shapes are Circular
These 2 statements are conflicting with each other, how can the inner layer land shape be the same as the outer layer if it has to be circular ? The outer layer land shape could be square.

To me it's obvious, the inner layer lands are always the same shape as the outer layer lands unless you deliberately change them to be something else, the default shape (unless there are overriding factors that require otherwise) is for the inner layer land to be circular.
But it does not read as I have written it - it just reads conflicting. :)


Posted By: Tom H
Date Posted: 05 Oct 2015 at 4:18am
Since the beginning g of multilayer PCB layout back in the 1970's the outer layer Pin 1 pad shape was square to indicate the Polarity Marking because there was no silkscreen. Otherwise all pad stacks would be round throughout the entire PC board.
 
There was no need to take up valuable board real-estate with square corner pads on the inner layer because you cannot see them anyway.
 
10 years later when CAD tools started to become popular the trend continued and that is the way Pin 1 pad stacks are created. i.e.: there is no other use for outer layer square pads than to indicate polarity and that is the "Default Pad Stack".
 
Rookie designers ask these types of legitimate questions and the old timers have to explain: "Because that's the way it's always been done" (even though it breaks a pad stack naming convention rule in order to simplify the pad stack name).  Confused  We're not going to break rank on this issue.
 


-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: Matthew Lamkin
Date Posted: 05 Oct 2015 at 4:27am
Cheers Tom,

So now I am being told your document should be changed as it is your document that is saying that they should be the same shape as on the outer layers.
Which is contrary to both what you have explained and that the 2nd item suggests.

They are either matching the outer layer shape or they are round.

Inner
Layer Land is the same shape as the outer layer land
contradicts:
The inner layer land shapes are Circular

Because if the outer layer land is square and the inner layer land is the same shape as per the first default then it cannot be round as per the 2nd default.

What is being suggested is that your statements in that are conflicting & hence confusing - perhaps the first one should not be used?


Posted By: Tom H
Date Posted: 05 Oct 2015 at 4:38am
I guess we'll have to change the document to clarify the rule. Thanks for the heads up.
 
A square pad on an inner layer is useless.
 


-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: Matthew Lamkin
Date Posted: 05 Oct 2015 at 4:39am
Thumbs Up
Cheers Tom.



Posted By: jameshead
Date Posted: 05 Oct 2015 at 5:45am
Another example of padstyle of the top "layer 1" may be different to the inner and bottom layers is a TO-220 horizontal where you have a rectangular pad to connect with the heatsink of the device and have only a round pad on inner and the bottom layer.

I've interpreted the standard to have:

r1599_1039r25o510xc580zc580h385

Rectangular 15.99 mm x 10.39 mm, radius 0.25 mm corners for a pad on layer 1, where the centre of the rectangular pad is off-set 5.1 mm from the centre of the hole.  Hole size is 3.85 mm.   Pads on inner layers and the bottom size is a round 5.80 mm.

Not all CAD systems allow you do this easily though.


Posted By: AleksMK
Date Posted: 29 Apr 2020 at 6:50am
Hi everyone,

I have a question on the use of the special x modifier. This is it's definition:

"x = Special modifier used alone or following other modifiers for lands on opposite side to primary layer land dimension"

And later on there are three examples:

mxc = Solder Mask Opposite Side Circular

mx0 = Solder Mask Opposite Side No Solder Mask

xc = Opposite Side Circular


As the x-modifier is defined that it is following other modifier, is the last "xc" example wrong? Should it not be "cx"?


I need to create a padstack, which will have a circular land patter on the bottom layer only 1.2mm in size, with a solder mask on the bottom layer only with 1.3mm opening and no bottom paste mask layer. Which of the following namings (or none?) will be the correct one for this padstack?


1. cx120mx130px0

2. xc120mx130px0

3. xc120xm130xp0


Thanks!

Aleks




Posted By: Tom H
Date Posted: 29 Apr 2020 at 7:31am
AleksMK, do you have a copy of the pad stack naming convention document? 

You can download it here - http://www.pcblibraries.com/downloads " rel="nofollow - www.pcblibraries.com/downloads 



-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: AleksMK
Date Posted: 29 Apr 2020 at 7:56am
Hi Tom,

Yes, I do have the document, the question arose from reading that document.  As I quoted, It's not very clear to me how the naming for my padstack should be? Any advice on that?

Thanks!
Aleks


Posted By: Tom H
Date Posted: 29 Apr 2020 at 9:34am
There is a pad stack naming issue with the current V2019 Library Expert for SMD pads that are defined on both the Top and Bottom layers. This issue will be fixed in V2020 coming out next month. 

To create a complex pad stack, you need the FP Designer feature and that does not come with the free Library Expert Pro (yet), but next month when V2020 is released, the Library Expert Pro will have 100% full featured program (just like the Enterprise version) and support these CAD tools - 

  1. CADint
  2. DesignSpark
  3. DipTrace
  4. Eagle
  5. KiCad
  6. Pantheon
  7. Proteus
  8. Pulsonix
  9. McCAD
  10. SoloPCB
  11. Target 3001!
  12. Ultiboard
So even if you don't use any of these CAD tools you can still download the program for free and use it as an advanced Land Pattern Calculator. 

Also, starting next week we start giving away the full featured Library Expert Enterprise for free. Just pay the yearly maintenance to get all the updates and technical support for the year. Pick any CAD tool and get our new Cloud License for a yearly lease at 20% of list price. 

Bottom line is that you need FP Designer to create custom pad stacks and we're either going to give that away for free or lease it at an affordable price point. 

The software program needs to work perfect to take away any guessing and confusion. 

Also, putting a SMD pad on the top & bottom layers is rare. What application is this for?



-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: AleksMK
Date Posted: 29 Apr 2020 at 9:44am
Hi Tom,

Thanks for all the info, although a bit unrelated to my question :-) The application for which I need this padstack is creating test points in OrCAD PCB Designer Professional, where the padstack need to be defined on the layer where you are creating the test point. So if I want a test point on the bottom layer, I need to have the bottom layer defined in my padstack. The padstack is not being mirrored when adding testpoints, hence this requirement.

If I may re-iterate my question: using the padstack naming convention that I have downloaded from PCB Libraries, what is the correct name to name a padstack which will have a circular land patter on the bottom layer only 1.2mm in size, with a solder mask on the bottom layer only with 1.3mm opening and no bottom paste mask layer?

Cheers


Posted By: Tom H
Date Posted: 29 Apr 2020 at 10:08am

Modifiers that are used when pad stack features are different than the defaults

In instances where shapes are different this becomes a two letter code with the "modifier" first followed by the land shape letter.

x = Special modifier used alone or following other modifiers for lands on opposite side to primary layer land dimension 

So the "x" comes before the shape character. 



-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn


Posted By: AleksMK
Date Posted: 29 Apr 2020 at 10:43am
Thanks! So I will name my padstack xc120mx130px0.

Cheers!
Aleks


Posted By: Tom H
Date Posted: 07 Apr 2024 at 2:30pm
Updated Pad Stack Naming Convention released in IPC-7352. 

The first letter in the pad stack name describes the shape of the pad on the outer layers of the circuit board. Small letters are used. Note: “b” = Oblongs, because the letter “o” could easily be confused with the number “0”. 





-------------
Stay connected - follow us! https://twitter.com/PCBLibraries" rel="nofollow - X - http://www.linkedin.com/company/pcb-libraries-inc-/" rel="nofollow - LinkedIn



Print Page | Close Window