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Another interesting observation on manufacturer recommended patterns is that most of the recommended patterns do not use min/max technology for pad stack calculation.
It seems the many component manufacturers use Nominal package dimensions and simply add a Toe, Heel and Side solder joint. This is typically true for most chip components.
IPC-7351 and 7352 use a min/max mathematical model. This includes the component package and terminal tolerances. The resulting pad stack pattern is capable of handling accurate assembly attachment when the component package comes in the minimum, nominal or maximum material condition.
The main point is that many component manufacturers provide robust package and terminal tolerances, but the recommended pattern that they publish in their datasheets will not accommodate a component that is delivered in the minimum or maximum material condition.
This issue sheds light on the accuracy or necessity of component mfr. tolerances. Are they realistic? And if so, why don't the publish patterns that will accommodate min/max condition components?
Here is an example of a 1206 capacitor from Murata. Part Number: GRM31CC72A475KE11L Case Code: GRM31C Datasheet: https://search.murata.co.jp/Ceramy/image/img/A01X/G101/ENG/GRM31CC72A475KE11-01A.pdf " rel="nofollow - https://search.murata.co.jp/Ceramy/image/img/A01X/G101/ENG/GRM31CC72A475KE11-01A.pdf
Here are the package dimensions. every value has a 0.30 mm tolerance.
Here is the manufacturer recommended footprint:
Here is the footprint using Nominal Package dimensions and the mfr. pattern. Notice the terminals are off the pad stack. No Heel.
Here is the minimum package material condition according to the tolerances and the mfr. recommended pattern. The terminals are way off the pad stack. No Heel.
Here is the maximum package material condition according to the tolerances and the mfr. recommended pattern. No Heel and minimum Side fillet.
The mfr. recommended pattern does is not compatible when the component package comes in minimum, nominal or maximum material condition.
Try this out with your chip manufacturer recommended patterns to ensure that the pad stacks will accommodate a package in all material conditions. If not, the package and terminal tolerances could be too robust.
The FED Standard 'Volume 18' for The New Proportional Land Dimensioning Concept highly recommends not to use any mfr. package tolerances. Just use Nominal package dimensions and add a fixed Toe, Heel and Side.
Purchase the FED Volume 18 here for 30 Euros: https://www.fed.de/wissensdatenbank/detail/the-new-proportional-land-dimensioning-concept/" rel="nofollow - https://www.fed.de/wissensdatenbank/detail/the-new-proportional-land-dimensioning-concept/
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