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Third Placement Outline

Printed From: PCB Libraries Forum
Category: PCB Footprint Expert
Forum Name: Questions & Answers
Forum Description: issues and technical support
URL: https://www.PCBLibraries.com/forum/forum_posts.asp?TID=2482
Printed Date: 22 Nov 2024 at 6:31pm


Topic: Third Placement Outline
Posted By: jmeinert
Subject: Third Placement Outline
Date Posted: 10 May 2019 at 11:32am
I am getting three placement outlines on chips with Mentor Graphics. I get the normal courtyard and component outlines, with an additional circle in the middle of the part with placement outline and height.
 
version 2019.2



Replies:
Posted By: Tom H
Date Posted: 10 May 2019 at 12:23pm
These are the outlines that Library Expert produces and you have control in Preferences > Drafting to turn them on/off with either check boxes or by turning the line width value to 0.00. 
  1. Legend (silkscreen, trimmed around pins)
  2. Assembly (closed polygon)
  3. Component (using nominal dimensions)
  4. Terminals (where the Terminal Metal touches the pad)
  5. Courtyard
All of these go to different layers and are used for different applications. 

Only the Legend is printed on the PCB. 

The Assembly is used for a drawing. 

The Courtyard is used for placement aid. 

The Component and Terminal outlines should go on the same layer as they represent the physical package in the nominal material condition. 



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Posted By: jmeinert
Date Posted: 14 May 2019 at 9:08am
My Drafting setting are the same in 2019.02 as 2018.09. It looks as though the circle of the origin is being identified as a placement outline. 


Posted By: Tom H
Date Posted: 14 May 2019 at 9:33am
The Origin Marker and Courtyard are on the same layer because they are both used for placement guides and they don't go out to fabrication and assembly. 

This has been this way for the past 20 years. 

The only way to fix it in V2019.03 is to turn off the origin marker in Preferences > Drafting > Courtyard.

You can manually add an origin marker on the assembly layer, but then they would appear in the assembly drawing. 



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