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Does Capacitor Height Affect Pad Geometry?

Printed From: PCB Libraries Forum
Category: PCB Footprint Expert
Forum Name: Questions & Answers
Forum Description: issues and technical support
URL: https://www.PCBLibraries.com/forum/forum_posts.asp?TID=2366
Printed Date: 22 Nov 2024 at 7:03pm


Topic: Does Capacitor Height Affect Pad Geometry?
Posted By: ckhalleran
Subject: Does Capacitor Height Affect Pad Geometry?
Date Posted: 24 Jul 2018 at 9:50am
I'm trying the latest version of Expert Pro. When making footprint for chip capacitors, I'm not seeing much (if any) difference in the pad size and toe-span in the footprint, after importing into Altium. 

I tried making footprints for 0805 caps, 1210 caps, 1812 caps... and I never got the feeling that increasing the component height actually had an affect on the pad dimensions. 

Am I doing something wrong? Is there a minimum package size for caps, where anything beneath that size, the height of the cap doesn't make much difference? 

I was using "M" density, but I also tried "N". 

Thanks, 
Chris


Replies:
Posted By: Tom H
Date Posted: 24 Jul 2018 at 10:37am
According to IPC-J-STD-001, the height of a chip component does impact the "Toe" solder joint goal. 

Minimum Solder Joint Fillet Height = 25% of package Height or 0.50 mm, whichever is less. So the maximum required fillet = 0.50 mm regardless of the package height. 

But the solder joint goal tables in Library Expert already compensate for this as there are different Toe values for every chip size 01005, 0201, 0402, 0603, 0805, 1206, etc. by taking into account the maximum height for each chip size to insure that the fillet equals at least 25% of the package height. 

When all these calculations are programmed into Library Expert, it meets or beats the IPC-J-STD-001 requirements for solder joint goals. So, when you enter different package heights for a chip component, you will not see any difference in the pad size calculation. 



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Posted By: dbrgn
Date Posted: 03 Feb 2019 at 6:12am
If I interpret IPC7351 correctly, then the design approach for chip components is using the actual exposed lead size and adding toe/heel/side fillets to that.

In the tables for those fillets there are no values that depend on the height though:

https://tmp.dbrgn.ch/screenshots/20190203140804-kcj4n7hs.png" rel="nofollow - https://tmp.dbrgn.ch/screenshots/20190203140804-kcj4n7hs.png

Are there any guidelines regarding the footprint size in relation to height in IPC7351? Unfortunately I still have the original version of the standard, not B (or C which is still unreleased), maybe those instructions were added in the B revision... The original standard doesn't even seem to make differentiate between capacitor and resistor land patterns.

Posted By: Tom H
Date Posted: 03 Feb 2019 at 8:55am
According to IPC-J-STD-001, the chip package fillet height should be 25% of the package height or 0.50 mm, which ever is greater. 

IPC-7351 does not really follow the guidelines established in IPC-J-STD-001 and that is the ruling document for solder joint acceptability. 

Use IPC-J-STD-001  as your standard and 7351 as your guideline. 



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