Chip Component Package Tolerances

Every aspect of a PCB mounted component has tolerances. These include tolerances for Package length/width and terminals. The IPC-7351B refers to a mathematical model that also includes fabrication and assembly tolerances. IPC-7352 removed the manufacturing tolerances from the mathematical model.

The mathematical model takes into consideration the minimum and maximum package dimensions to ensure that the resulting land pattern accommodates the package tolerance range. Tolerances are referred to as Min/Max technology meaning the pad stack size and spacing regardless of if the component package comes in the minimum or maximum material condition.

Since the package and terminal tolerances affect the resulting pad stack size and spacing, robust tolerances will produce larger pad stacks while no tolerances will produce pad stacks that are too small. The IPC-7351 Side solder joint goal for chip packages is zero. The pad width is the same dimension as the Maximum terminal lead width.

The Heel solder joint goal for chip packages is zero. The heel is determined by the terminal lead and package length tolerances.

The Toe normally has a solder joint goal has a predefined value. Then the terminal lead and package length tolerances are added to the Toe value. The resulting Toe solder joint is a combination of the Toe goal value and terminal and package length tolerances.

Here are the recommended tolerances for the various chip case codes:

• 01005 – 0.02 mm
• 0201 – 0.03 mm
• 0402 – 0.05 mm
• 0603 – 0.10 mm
• 0805 – 0.15 mm
• 1206 and higher – 0.20 mm

Different component manufacturers will publish a wide range of tolerances. For example, Panasonic, Yageo, Vishay, AVX, Murata, Kemet and Taiyo Yuden will have different tolerances to the same Case Code. But the PCB designer or CAD librarian want one set of tolerances for each Case Code.

Here is a 0603 Chip with no tolerances: 

Here is a 0603 Chip with a 0.05 tolerance on Length, Width and Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.10 tolerance on Length, Width and Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.15 tolerance on Length, Width and Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.20 tolerance on Length, Width and Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.25 tolerance on Length, Width and Terminal Nominal Density Level:

Here is a 0603 Chip with a 0.10 tolerance on Length, Width and Terminal Least Density Level:

Here is a 0603 Chip with a 0.10 tolerance on Length, Width and Terminal Most Density Level:

Chip component manufacturers do not use their package tolerances when publishing their manufacturer recommended patterns. They use nominal package dimensions and add a toe, heel and side solder joint regardless of how robust their tolerances are. If component tolerances are real and component packages can be shipped to assembly shops and some come in the minimum material condition and some come in the maximum material condition, there will be assembly attachment issues.

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