Auto-generate Pin 1 Indicator Line

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Hi guys, We have just purchased our licenses for Library Expert having waded in the legacy of LP Wizard for many years....good to be back on track again.
I am setting up our Preferences file as to how we wish our components to appear and have found some  inconsistency with the "Auto generate Pin 1 Indicator Line" Vs Silkscreen/Legend Dot.  
I understand that the "Auto generate Pin 1 Indicator Line" is new to the proposed IPC-7351 Iss.C, where as the 'Dot' has been around for years, but takes up valuable room etc, so we would like to take advantage of using this new feature.

Your default preference file that is supplied in the generic 'Drafting/Legend' tab, has neither function 'activated', so I activated the "Auto generate Pin 1 Indicator Line" only.

Unless I'm blind and not looking correctly, I was surprised to see that the following Component families do not appear to create a Pin 1 Indicator Line:- BGA, CGA, LGA, Pullback QFN & Pullback QFN with Tab. (All of these will create a Pin 1 Dot) 

The DFN 2 pin 'Demo' does not create a "Pin 1 Indicator Line", but does create a Pin 1 Dot and a Chamfer outline on the Assembly layer, There is a warning that device is too small for Silk Screen?

There is also inconsistency with Side Concave Package (4pin), the following will create a Pin 1 Dot, but not a "Pin 1 Indicator Line", Capacitor, Crystal, Fuse, Inductor, Resistor. Only the Diode & LED create both.

Thanks.

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Tinytroll Members Profile Send Private Message Find Members Posts Add to Buddy List New User Joined: 04 Feb 2016 Status: Offline Points: 2	Post Options Post Reply Quote Tinytroll Report Post Thanks(0) Quote Reply Topic: Auto-generate Pin 1 Indicator Line Posted: 21 Nov 2019 at 7:13am
	Hi guys, We have just purchased our licenses for Library Expert having waded in the legacy of LP Wizard for many years....good to be back on track again. I am setting up our Preferences file as to how we wish our components to appear and have found some inconsistency with the "Auto generate Pin 1 Indicator Line" Vs Silkscreen/Legend Dot. I understand that the "Auto generate Pin 1 Indicator Line" is new to the proposed IPC-7351 Iss.C, where as the 'Dot' has been around for years, but takes up valuable room etc, so we would like to take advantage of using this new feature. Your default preference file that is supplied in the generic 'Drafting/Legend' tab, has neither function 'activated', so I activated the "Auto generate Pin 1 Indicator Line" only. Unless I'm blind and not looking correctly, I was surprised to see that the following Component families do not appear to create a Pin 1 Indicator Line:- BGA, CGA, LGA, Pullback QFN & Pullback QFN with Tab. (All of these will create a Pin 1 Dot) The DFN 2 pin 'Demo' does not create a "Pin 1 Indicator Line", but does create a Pin 1 Dot and a Chamfer outline on the Assembly layer, There is a warning that device is too small for Silk Screen? There is also inconsistency with Side Concave Package (4pin), the following will create a Pin 1 Dot, but not a "Pin 1 Indicator Line", Capacitor, Crystal, Fuse, Inductor, Resistor. Only the Diode & LED create both. Thanks.



Tom H Members Profile Send Private Message Find Members Posts Add to Buddy List Admin Group Joined: 05 Jan 2012 Location: San Diego, CA Status: Offline Points: 5718	Post Options Post Reply Quote Tom H Report Post Thanks(0) Quote Reply Posted: 21 Nov 2019 at 7:48am
	Congratulations and good to have you back on track again with Library Expert. The Preferences are filled with rules that you cannot violate. If a rule is violated, certain things happen. Example: You set your Silkscreen Legend Line Width, Clearance and map to Max., Nom. or Min. body in the drafting tab. Then when you create a part that is too small to meet all those rules nothing happens or you get a message "Geometry is too small for Legend outline". There are 2 ways to add a Legend Outline and save it to FPX file. Use Drafting Outlines to insert a full Rectangle around the footprint. Select the "Draw Symbol" drop down icon in the Calculator toolbar. This allows you to insert a shape on multiple layers or a Keep-out. Select Drafting Symbols. Then the upper left drop down box you can select 8 different shapes and Rectangle is one option. Insert the Length and Width and Line Width and select Apply. Adjust the values until you get what you like and select Apply every time you change the values. When you're finished, select "Close". Do the same if you want to insert any of the shapes. Watch this short video for so tips. http://www.pcblibraries.com/products/fpx/userguide/default.asp?ch=9.3 Move the part to FP Designer and Library Expert will automatically add Silkscreen Legend around the part. Here are some of the shapes in the Drafting Outlines: The Pin 1 indicator Line can only be used on component families where the terminal leads are outside the package (like Gull Wing and J-Lead) and not underneath the package. Sounds like you can use a free webcast training on Library Expert to ask all your questions and get all of then answered. There are hundreds of features that many people do find for a long time unless you have proper training or watch all 70 videos in the Help > Topics > Contents or the on-line User Guide - http://www.pcblibraries.com/products/fpx/userguide/
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Tom H Members Profile Send Private Message Find Members Posts Add to Buddy List Admin Group Joined: 05 Jan 2012 Location: San Diego, CA Status: Offline Points: 5718	Post Options Post Reply Quote Tom H Report Post Thanks(0) Quote Reply Posted: 21 Nov 2019 at 8:01am
	I moved this post from Bugs to Q & A forum. This is not a bug, it's a feature.
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