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Nominal Epad vs Max Epad
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lsday View Drop Down
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    Posted: 17 Sep 2019 at 12:15pm
Question: Why does the Library Expert calculate the Exposed center pad padstack to nominal instead of max?
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Tom H View Drop Down
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Points: 5719 		Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 17 Sep 2019 at 12:37pm
Several reasons:
  1. Most component manufacturer's recommended land pattern use the Nominal dimensions for the Thermal Pad size. This is probably the most important reason. 
  2. There is a Rule of 0.20 mm gap between the Signal Pads and the Thermal Pad. Many times when you make the Thermal Pad Maximum, it violates this rule. When the Spacing Rule is violated, Library Expert will alert you that it's trimming the Signal Pads to obey the Spacing Rule.
  3. Most component manufacturer's make the Thermal Tab Nominal or less. It's very rare that it comes in the MMC. 
  4. If the Thermal Pad is Maximum and the solder volume is 60%, there's more solder than what's required to secure the Thermal Tab to the PCB. This also creates solder voids. 
  5. Excess (to much) Pad allows the package to float around during reflow oven. The main goal is to prevent package movement during assembly to achieve the best soldering result. This is why the component mfr.'s recommend the nominal pad size. The manufacturer builds extensive test boards and reference designs. 
You need to show us a component mfr. datasheet that recommends a maximum pad size. We built 2 million parts for POD and could not find any mfr. using Maximum pad size dimensions. 
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lsday View Drop Down
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Points: 24 		Post Options Post Options   Thanks (0) Thanks(0)   Quote lsday Quote  Post ReplyReply Direct Link To This Post Posted: 17 Sep 2019 at 1:44pm
Thank you for your response. The old LP Wizard calculated them to max and we still have cells with those size pads. We also still use land patterns per JEDEC OUTLINES. We do not create cells for every vendor. We reuse if we think it fits.
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Tom H View Drop Down
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Points: 5719 		Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 17 Sep 2019 at 2:12pm
We (PCB Libraries, Inc.) created LP Wizard back in 2004. 

Library Expert allows the user to enter any dimensional data that you want, both for the physical component and the Land Pattern. 

The end user has options to oversize, under-size or exact size. Whatever you want. 

No component manufacturer uses JEDEC package dimensions verbatim. We already proved that via our research. 

JEDEC seems to be like a Guideline. 
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Points: 24 		Post Options Post Options   Thanks (0) Thanks(0)   Quote lsday Quote  Post ReplyReply Direct Link To This Post Posted: 17 Sep 2019 at 2:58pm
Yes you are correct about Jedec and vendors. Thanks Tom!
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Points: 3 		Post Options Post Options   Thanks (0) Thanks(0)   Quote cc_ds Quote  Post ReplyReply Direct Link To This Post Posted: 26 Nov 2019 at 5:35am
Originally posted by Tom H Tom H wrote:

You need to show us a component mfr. datasheet that recommends a maximum pad size. We built 2 million parts for POD and could not find any mfr. using Maximum pad size dimensions. 

I found a part from On Semiconductor: CAT24C64HU4I−GT3
In the datasheet they show a recommended land pattern.
There the EP pad dimension is larger than the max values.

In the same datasheet they also reefer to another document.
And there they write:

Originally posted by Onsemi Onsemi wrote:

Based on the case outline’s “nominal” package footprint dimensions, the PCB mounting pads need to be larger than the nominal package footprint
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Tom H View Drop Down
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Points: 5719 		Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 26 Nov 2019 at 9:51am
Some electronic semiconductors generate more Heat than others. Therefore, the mfr. will recommend a larger thermal pad than nominal.

This happens a lot in Texas Instruments recommended patterns.

Listen the mfr.

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Points: 3 		Post Options Post Options   Thanks (0) Thanks(0)   Quote cc_ds Quote  Post ReplyReply Direct Link To This Post Posted: 27 Nov 2019 at 3:26am
The part I'm looking at is a EEPROM, very low heat dissipation.
On Semiconductor: CAT24C64HU4I−GT3

The reasons you list above are a good argument to use nominal values.
I find it surprising why manufacturer would recommend EP pad size larger than max value.

Would you recommend to use the manufacturer recommended land patter for this part?
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Tom H View Drop Down
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Points: 5719 		Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 27 Nov 2019 at 9:06am
The component mfr. creates a reference design to test the circuitry and heat flow.   

They also create a PCB with multiple land patterns and run shock, vibration and thermal cycle tests. The last part on the PCB is the land pattern they recommend.

Not every mfr. does this, but how do you know which one did.

Since IPC never created any test boards to validate the 7351 guideline for solder joint goals there is no conclusive evidence that the solder joint goals in the guideline are optimized for the best assembly attachment.

However, there was a lot of highly educated guesses but after taking the IPC-J-STD-001 training course and CIT certification, I found out that 7351 does not adhere to the J-STD-001 solder joint goal acceptance for assembly.

So, I tend to use the mfr. recommended pattern, hoping they ran the necessary tests so that my PCB has the best performance.

IPC-7351 is good for when the mfr. does not provide a recommended pattern.

Also, I always use the recommended pattern for all connectors and non-standard packages.
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