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  <pubDate>Tue, 28 Apr 2026 23:30:35 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : Trimming heels under the component body]]></title>
   <link>https://www.PCBLibraries.com/forum/trimming-heels-under-the-component-body_topic12_post14522.html#14522</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Trimming heels under the component body<br /><strong>Posted:</strong> 27 Apr 2026 at 8:32am<br /><br />The link is for a paper that I wrote when I was employed by Mentor Graphics in 2010.&nbsp;<div><br></div><div>Siemens took it down.&nbsp;</div><div><p ="xxms&#111;normal">Minimum Trim Standoff: <o:p></o:p></p><ul style="margin-top:0in" ="disc"> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Only affects Gullwing Leads the A1 dimension <o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Dieter Bergman said pad trimming is not an IPC-7351 Standard</span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">IPC J-STD-001 says that pads under low profile parts with A1     dimension is 0.00 should be trimmed for plastic body packages<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">The default setting is 0.03 meaning that any A1     dimension less than 0.03 will get trimmed<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">The trimming is to the Nominal Package Body dimension<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Many people turn it off by entering a value of 0.00<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Some people tone it down to 0.01 so that it only     affects part with A1 being 0.00<o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">The main reason for customers who requested this     feature was to compensate for component manufacturers to limit their ‘L’     tolerance. In most 1.27 mm pitch SOICs, the ‘L’ dimension is min 0.41 and     max 1.27. The tolerance is +/-0.43. <o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">Today, component manufacturers have a maximum ‘L’     tolerance of +/- 0.25 and a nominal tolerance of +/- 0.15. <o:p></o:p></span></li> <li ="xxms&#111;normal" style="mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:       &quot;Times New Roman&quot;">See the attached TI Case Code D0008A. the ‘L’ tolerance     is +/- 0.43 which is too robust so Texas Instruments Recommended Pattern     trims the pad from going under the package.</span></li></ul><p ="xxms&#111;normal">Summary: if the ‘L’ tolerance is +/- 0.15 there’s no needfor trimming. Even component manufacturers don’t use their ‘<b>L’ </b>tolerance fortheir pad stack calculation. A ‘<b>L</b>’ tolerance of 0.43 is way too robust, but inthe 1980s and 1990s the ‘<b>L</b>’ tolerance was +/- 0.43 but today it’s +/- 0.15. Thelarge ‘<b>L</b>’ tolerance is the only reason for Minimum Trim Standoff Height.</p><p ="xxms&#111;normal">I hope this explains the issue.</p><p ="xxms&#111;normal"><br></p><br></div>]]>
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   <pubDate>Mon, 27 Apr 2026 08:32:08 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : Trimming heels under the component body]]></title>
   <link>https://www.PCBLibraries.com/forum/trimming-heels-under-the-component-body_topic12_post14521.html#14521</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=11979">m.elsayed</a><br /><strong>Subject:</strong> Trimming heels under the component body<br /><strong>Posted:</strong> 27 Apr 2026 at 4:59am<br /><br />Thanks,&nbsp;<div><br></div><div>I have touched this point and try use the explanation here to understand point, however I notice the below link doesn't work.&nbsp;</div><div><br></div><div>Can provide working link please to check it's content.</div><div><br></div><div><a href="http://communities.mentor.com/mgcx/servlet/JiveServlet/download/28883-8838/PCB%20Design%20Optimizati&#111;n%20Starts%20in%20the%20CAD%20Library.pdf" target="_blank" rel="nofollow">http://communities.mentor.com/mgcx/servlet/JiveServlet/download/28883-8838/PCB%20Design%20Optimization%20Starts%20in%20the%20CAD%20Library.pdf</a><div><br></div></div>]]>
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   <pubDate>Mon, 27 Apr 2026 04:59:32 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : 0201 Capacitor Corner Radius Pad]]></title>
   <link>https://www.PCBLibraries.com/forum/0201-capacitor-corner-radius-pad_topic3631_post14503.html#14503</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=15739">dramos</a><br /><strong>Subject:</strong> 0201 Capacitor Corner Radius Pad<br /><strong>Posted:</strong> 08 Apr 2026 at 9:12am<br /><br />Hi Tom and Team,<div><br></div><div>Thanks for the clarification, when you mentioned length , width I was surprised if you were referring to any of the values. I was a little bit in shock!! hahahahaha</div><div><br></div><div>Thanks and regards,</div><div>david</div>]]>
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   <pubDate>Wed, 08 Apr 2026 09:12:08 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : 0201 Capacitor Corner Radius Pad]]></title>
   <link>https://www.PCBLibraries.com/forum/0201-capacitor-corner-radius-pad_topic3631_post14501.html#14501</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 0201 Capacitor Corner Radius Pad<br /><strong>Posted:</strong> 08 Apr 2026 at 8:41am<br /><br />0402 is not 'Less than 1.00 mm'.&nbsp;<div><br></div><div>It looks OK with a 0.10 mm corner radius.&nbsp;</div><div><br></div><div><img src="uploads/3/0402_Capacitor_2026-04-08_08-38-41.png" height="288" width="490" border="0" /><br></div><div>&nbsp;</div><div>Watch out for excessive package tolerances.&nbsp;</div><div><br></div><div>This package is 1.00 L x 0.50 W x 0.55 H with a 0.10 tolerance on all dimensions.&nbsp;</div><div><br></div>]]>
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   <pubDate>Wed, 08 Apr 2026 08:41:07 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : 0201 Capacitor Corner Radius Pad]]></title>
   <link>https://www.PCBLibraries.com/forum/0201-capacitor-corner-radius-pad_topic3631_post14499.html#14499</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=15739">dramos</a><br /><strong>Subject:</strong> 0201 Capacitor Corner Radius Pad<br /><strong>Posted:</strong> 08 Apr 2026 at 2:59am<br /><br />Hi Tom and Team,<div><br></div><div>Many thanks for your fast response.&nbsp;</div><div><br></div><div>Does it mean that we should apply the same rule of thumb to 0402 case components or even 0603 components? I am thinking on resistors ...</div><div><br></div><div>Thanks for spreading your knowledge :)</div><div>david</div>]]>
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   <pubDate>Wed, 08 Apr 2026 02:59:53 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : 0201 Capacitor Corner Radius Pad]]></title>
   <link>https://www.PCBLibraries.com/forum/0201-capacitor-corner-radius-pad_topic3631_post14498.html#14498</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 0201 Capacitor Corner Radius Pad<br /><strong>Posted:</strong> 07 Apr 2026 at 8:30am<br /><br />Rule of thumb - any package less than 1.00 mm in length or width should have 0.05 mm corner radius pads.&nbsp;<div><br></div><div>You can use the 'SMD Pad Stack Rules' in the side panel of the calculator to change the corner radius.&nbsp;</div><div><br></div><div>Or you can move the calculator footprint to FP Designer to permanently save the 0.05 mm corner radius to FPX library format. But we recommend that you first setup everything in the calculator before moving to FP Designer so you won't have to edit the pad stack in FP Designer.&nbsp;</div><div><br></div><div>FP Designer saves all your settings to the FPX library. You can rename the Footprint Name in the Library Editor.&nbsp;</div><div><br></div>]]>
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   <pubDate>Tue, 07 Apr 2026 08:30:25 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : 0201 Capacitor Corner Radius Pad]]></title>
   <link>https://www.PCBLibraries.com/forum/0201-capacitor-corner-radius-pad_topic3631_post14497.html#14497</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=15739">dramos</a><br /><strong>Subject:</strong> 0201 Capacitor Corner Radius Pad<br /><strong>Posted:</strong> 07 Apr 2026 at 4:09am<br /><br />Hi all,<div><br></div><div>I created my first 0201 capacitor and I feel that using a Corner Radius Size Limit parameter= 0.10 mm could be "risky" (I used Fab Tol= 0, Placement Tol=0).</div><div><br></div><div><img src="uploads/15739/cap0201.png" height="455" width="900" border="0" /><br></div><div><br></div><div>I know that some manufacturers use 0.05 mm.</div><div><br></div><div>My component is&nbsp;GRM033R61C104KE14D from Murata</div><div><br></div><div>Which is your recommendation for this tiny component sizes?</div><div><br></div><div>Waiting for your comments.</div><div><br></div><div>David</div><div><br></div><div><br></div>]]>
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   <pubDate>Tue, 07 Apr 2026 04:09:03 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : IPC-735x Evolutions]]></title>
   <link>https://www.PCBLibraries.com/forum/ipc735x-evolutions_topic3576_post14324.html#14324</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> IPC-735x Evolutions<br /><strong>Posted:</strong> 19 Nov 2025 at 10:16am<br /><br />The unreleased IPC-7351C had new solder joint goal tables for Gull Wing and Rectangular or Square End Cap packages.&nbsp;<div><br></div><div>The Square End Cap solder joint goals need to have unique Toe values for every chip size.&nbsp;</div><div><br></div><div><img src="uploads/3/Solder_Joint_Goals_for_Chips.png" height="169" width="1000" border="0" /><br></div><div>&nbsp;</div><div>The Gullwing terminal lead needs a different toe goal for every pin pitch.&nbsp;</div><div><br></div><div><img src="uploads/3/Gullwing_Toe_Calculati&#111;n.png" height="492" width="583" border="0" /><br></div><div>&nbsp;</div><div>SOP/QFP Table:</div><div><br></div><div><img src="uploads/3/Solder_Joint_Goals_for_Gullwing.png" height="179" width="1000" border="0" /><br></div><div>&nbsp;</div>]]>
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   <pubDate>Wed, 19 Nov 2025 10:16:31 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : IPC-735x Evolutions]]></title>
   <link>https://www.PCBLibraries.com/forum/ipc735x-evolutions_topic3576_post14323.html#14323</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=17148">sot23</a><br /><strong>Subject:</strong> IPC-735x Evolutions<br /><strong>Posted:</strong> 19 Nov 2025 at 9:05am<br /><br />Thank your for the answer.<div><br></div><div><i>"<span style=": rgb251, 251, 253;">IPC-7351B and IPC-7352 are identical for Surface Mount. No change except the pad stack naming convention added a double 'rr' for Rounded Rectangle pad shape."</span></i></div><div><span style=": rgb251, 251, 253;">That is not what I see when I read both documents side by side :&nbsp;</span></div><div><span style=": rgb251, 251, 253;">Table 3-3 (page 10) of the 7352 specify a Toe calculation for Square ends components with W=&lt;0.5mm that, on the Median footprint, is dependent of the height of the component (which I think totally makes sense when comparing to J-STD-001). This is not the case for the 7351 (table 3-5, page 17). As this height dependency is only for the N footprint, it leads to cases where the N pads are smaller than the L pads, which seems strange.</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><i><span style=": rgb251, 251, 253;">"</span><span style=": rgb251, 251, 253;">IPC-7352 introduced Through-hole technology, but most of the information was extracted from IPC-2221 &amp; IPC-2222."</span></i></div><div><span style=": rgb251, 251, 253;">The Through hole calculation (4.4.1, table 4-1 and 4-2) is in direct contradiction to the calculation in IPC 2222 (Table 9-5). Or I am having big trouble understanding theses tables.</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><span style=": rgb251, 251, 253;">Theses are mostly the points that confuses me.</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><span style=": rgb251, 251, 253;">Thank you for the linked posts. It is very interesting to know the history behind these standards.&nbsp;</span></div>]]>
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   <pubDate>Wed, 19 Nov 2025 09:05:14 +0000</pubDate>
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   <title><![CDATA[Footprints / Land Patterns : IPC-735x Evolutions]]></title>
   <link>https://www.PCBLibraries.com/forum/ipc735x-evolutions_topic3576_post14320.html#14320</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> IPC-735x Evolutions<br /><strong>Posted:</strong> 18 Nov 2025 at 8:56am<br /><br />IPC-7351B and IPC-7352 are identical for Surface Mount. No change except the pad stack naming convention added a double 'rr' for Rounded Rectangle pad shape.&nbsp;<div><br></div><div>IPC-7352 introduced Through-hole technology, but most of the information was extracted from IPC-2221 &amp; IPC-2222. The main thing that was added was the Through-hole land pattern naming convention which we created in 2008 but shelved until 2023.</div><div><br></div><div>The IPC-735x series misses the mark in several areas.</div><div><br></div><div>- Solder joint goals 'one size fits all' doesn't produce the best assembly attachment and it doesn't adhere to IPC J-STD-001. Also, the values between density levels is too robust. Most is too Most and Least is too Least.</div><div><br></div><div>- The naming convention puts the 'pin qty' at the end of the footprint name. This was changed in the IPC-7351C standard that was&nbsp;unanimously approved by the land pattern committee but never got released.&nbsp;</div><div><br></div><div>- The Zero Component Rotation differs from the standard they replaced - IPC-SM-782</div><div><br></div><div>Related posts:</div><div><br></div><div><a href="https://www.pcblibraries.com/forum/ipc7352-vs-pcb-libraries-footprint-naming-opti&#111;n_topic3488_post13869.html?KW=IPC%2D7352#13869" target="_blank" rel="nofollow">https://www.pcblibraries.com/forum/ipc7352-vs-pcb-libraries-footprint-naming-option_topic3488_post13869.html?KW=IPC%2D7352#13869</a></div><div><br></div><div><a href="https://www.pcblibraries.com/forum/pcb-pad-footprint-orientati&#111;n_topic3460_post14010.html?KW=IPC%2D7351B#14010" target="_blank" rel="nofollow">https://www.pcblibraries.com/forum/pcb-pad-footprint-orientation_topic3460_post14010.html?KW=IPC%2D7351B#14010</a></div><div><br></div>]]>
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   <pubDate>Tue, 18 Nov 2025 08:56:21 +0000</pubDate>
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