I would like to ask if you have a experience to have a X2 cap with big Pitch tolerances and It will not mounted properly in the PCB?

Is there any documents or computation for the slot to be use? 

Can any one help me on this? Kindly share your experience.

Thank you.

FP Designer now allows you to window select a row of pins or multiple rows of pins and group move in the 'X' or 'Y' direction. 

Glad you suggested this feature. 

But microminiature footprints might have the stencil thinned to 0.10 mm. 

IPC-7525C Stencil Design Guidelines is the leading document. 

Rounded Rectangle apertures help stencil release for lead-free solder alloys.

 

Stencil thickness is relevant since it is a factor in the volume of paste deposited, and the aperture area ratio/aspect ratio affecting paste release.

For example, I often see example stencil designs on Texas Instruments datasheets that are given for a 0.125mm stencil thickness.

SODFL is Flat Leads: 

BTC (Bottom Terminal Component) = QFN, SON, PQFN, PSON, BGA, LGA. CGA, etc.

Apologies for hijacking this thread, but I'd rather ask here then create a new thread for the same SODFL package type, if that is OK.

I have some difficulties classifying this type of components as to IPC standard (IPC-A-610J, class 3); mainly, is there a definite type to which they belong and I can check during PCB inspection? For instance, based on figures and specs I could classify as:

• Flat Gull wing leads -> mentions SOD (not SODFL specifically),
  
• Flat lug leads -> J version has added an image of LED (Figure 8-140), whilst pin looks similar to SODFL pin or
  
• BTC -> whilst image also look similar to SODFL pins (in regards to Figure 8-161)
  

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