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  <title>PCB Libraries Forum : Xpedition</title>
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  <pubDate>Fri, 10 Apr 2026 01:53:59 +0000</pubDate>
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   <title><![CDATA[Xpedition : Additional Settings for Xpedition Padstack Export]]></title>
   <link>https://www.PCBLibraries.com/forum/additional-settings-for-xpedition-padstack-export_topic3312_post13238.html#13238</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=17872">pildo</a><br /><strong>Subject:</strong> Additional Settings for Xpedition Padstack Export<br /><strong>Posted:</strong> 31 Aug 2023 at 9:30am<br /><br />Hello,<div><br></div><div>how can I define additional settings when generating outputs (Padstacks) for Siemens EDA - Xpedition?</div><div><br></div><div>Currently when generating Padstack.hkp files to be imported into EDM Librarian the names for PADs/HOLEs are very rudimentary and do not follow the Xpedtion naming scheme nor the IPC recommendation.</div><div><br></div><div>When generating an unencrypted ASCII export I've also noticed that the option "AUTO_GENERATED_NAME" is set for Holes which than isn't true.</div><div><br></div><div>Therefore now my question: How can I influence the definition of the pad/hole names and the additional settings as marked in the example?</div><div><br></div><div>Thanks.</div><div>Poldi</div><div><br></div><div>Example:</div><div>###################################</div><div><div>.FILETYPE PADSTACK_LIBRARY</div><div>.VERSION "02.00"</div><div>.CREATOR "PCB Libraries FPX Expert"</div><div>.DATE "Thursday, August 31, 2023 4:45:42 PM"</div><div><br></div><div>.UNITS MM</div><div><br></div><div>.PAD "<font color="#ff0000">Round 1.28mm</font>"</div><div>&nbsp;..ROUND</div><div>&nbsp; ...DIAMETER 1.28</div><div>&nbsp;..OFFSET (0, 0)</div><div><br></div><div>.PAD "<font color="#ff0000">Thermal 1.635mm</font>"</div><div>&nbsp;..4_WEB_ROUND_THERMAL_45</div><div>&nbsp; ...DIAMETER 1.635</div><div>&nbsp; ...TIE_LEG_WIDTH 0.307</div><div>&nbsp; ...THERMAL_CLEARANCE 0.1925</div><div>&nbsp;..OFFSET (0, 0)</div><div><br></div><div>.PAD "<font color="#ff0000">Round 1.635mm</font>"</div><div>&nbsp;..ROUND</div><div>&nbsp; ...DIAMETER 1.635</div><div>&nbsp;..OFFSET (0, 0)</div><div><br></div><div>.HOLE "<font color="#ff0000">Rnd 0.85</font>"</div><div>&nbsp;..ROUND</div><div>&nbsp; ...DIAMETER 0.85</div><div><font color="#ff0000">&nbsp;..POSITIVE_TOLERANCE 0.08</font></div><div><font color="#ff0000">&nbsp;..NEGATIVE_TOLERANCE 0.08</font></div><div>&nbsp;..HOLE_OPTIONS PLATED DRILLED <font color="#ff0000">AUTO_GENERATED_NAME</font></div><div>&nbsp;..DEPTH_ASSIGNMENT_METHOD THROUGH_HOLE</div><div>&nbsp;..DRILL_SYMBOL</div><div>&nbsp; ...ASSIGN_DURING_OUTPUT</div><div>&nbsp; &nbsp;....<font color="#ff0000">SIZE 1.5</font></div><div><br></div><div>.PADSTACK "c128h85"</div><div>&nbsp;..PADSTACK_TYPE PIN_THROUGH</div><div>&nbsp;..TECHNOLOGY "<font color="#ff0000">(Default)</font>"</div><div>&nbsp; ...TECHNOLOGY_OPTIONS NONE</div><div>&nbsp; ...TOP_PAD "Round 1.28mm"</div><div>&nbsp; ...INTERNAL_PAD "Round 1.28mm"</div><div>&nbsp; ...BOTTOM_PAD "Round 1.28mm"</div><div>&nbsp; ...CLEARANCE_PAD "Round 1.635mm"</div><div>&nbsp; ...THERMAL_PAD "Thermal 1.635mm"</div><div>&nbsp; ...TOP_SOLDERMASK_PAD "Round 1.28mm"</div><div>&nbsp; ...BOTTOM_SOLDERMASK_PAD "Round 1.28mm"</div><div>&nbsp; ...HOLE_NAME "Rnd 0.85"</div><div>&nbsp; &nbsp;....OFFSET (0, 0)</div></div><div>###################################</div>]]>
   </description>
   <pubDate>Thu, 31 Aug 2023 09:30:23 +0000</pubDate>
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   <title><![CDATA[Xpedition : Polarity for Capacitors, Text or Graphics?]]></title>
   <link>https://www.PCBLibraries.com/forum/polarity-for-capacitors-text-or-graphics_topic2202_post9082.html#9082</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=12412">JamesUS</a><br /><strong>Subject:</strong> Polarity for Capacitors, Text or Graphics?<br /><strong>Posted:</strong> 18 Aug 2017 at 7:29am<br /><br /><p align="LEFT" style="margin-bottom: 0cm"><font size="2"><font color="#000000" style=""><font style="">Polarizedcapacitors have large leakage current if the voltage is inverted.&nbsp;</font></font></font></p><p align="LEFT" style="margin-bottom: 0cm"><font size="2"><font color="#000000" style=""><font style="">Notall the capacitors are polarized, but when they are, it’s veryimportant not to mix their polarity up.&nbsp;</font></font></font></p><p align="LEFT" style="margin-bottom: 0cm"><font size="2"><font color="#000000" style=""><font style="">P</font></font><str&#111;ng style=""><font style=""><span style="font-weight: normal">olarity</span></font><font style="">indicates whether a circuit component is </font><str&#111;ng style=""><font style=""><span style="font-weight: normal">symmetric</span></font><font style="">or not.</font></strong></strong></font></p><p align="LEFT" style="margin-bottom: 0cm"></p>]]>
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   <pubDate>Fri, 18 Aug 2017 07:29:32 +0000</pubDate>
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   <title><![CDATA[Xpedition : Polarity for Capacitors, Text or Graphics?]]></title>
   <link>https://www.PCBLibraries.com/forum/polarity-for-capacitors-text-or-graphics_topic2202_post9081.html#9081</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Polarity for Capacitors, Text or Graphics?<br /><strong>Posted:</strong> 14 Aug 2017 at 4:17pm<br /><br />This question is for assembly shops and EE engineers. They have to deal with the silkscreen Legend that you provide them.&nbsp;<div><br></div><div>Personally, I like the graphic symbol plus "<b>+</b>" as it clearly defines the polarity for Polarized Capacitors.&nbsp;</div><div><br></div>]]>
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   <pubDate>Mon, 14 Aug 2017 16:17:34 +0000</pubDate>
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   <title><![CDATA[Xpedition : Polarity for Capacitors, Text or Graphics?]]></title>
   <link>https://www.PCBLibraries.com/forum/polarity-for-capacitors-text-or-graphics_topic2202_post9080.html#9080</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=10928">lsday</a><br /><strong>Subject:</strong> Polarity for Capacitors, Text or Graphics?<br /><strong>Posted:</strong> 14 Aug 2017 at 3:17pm<br /><br />What do most librarians use these day for the plus sign on Polarized Capacitors?&nbsp;<div><br></div><div>Is text good to use?&nbsp;</div><div><br></div><div>We use graphics, but am wondering about switching to text.</div><div><br></div>]]>
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   <pubDate>Mon, 14 Aug 2017 15:17:40 +0000</pubDate>
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   <title><![CDATA[Xpedition : Export Parts - Configuring Assigning Layers]]></title>
   <link>https://www.PCBLibraries.com/forum/export-parts-configuring-assigning-layers_topic1959_post8060.html#8060</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=532">chrisa_pcb</a><br /><strong>Subject:</strong> Export Parts - Configuring Assigning Layers<br /><strong>Posted:</strong> 15 Sep 2016 at 5:29pm<br /><br /><div>If you don't want something like Component Outline exported, that should be an option in FPX.</div><div><br></div><div>As per user-definable layers? The Expedition Ascii doesn't really support that. Everything is specific layer callouts, which is why they weren't settable in the first place. I mean, unless you turn them all into graphics, but I don't see the point. </div><div><br></div><div>As per putting out the Terminal Outline to a User Draft Layer? Those I could see turning into graphics. I can look into that. Right now it appears those are shifted to assembly outlines, which was probably sketchy in the first place. Having them be graphics on a user layer name&nbsp;specified seems reasonable, and if ASSEMBLY_OUTLINE is specified it gets shifted to assembly.</div><div><br></div>]]>
   </description>
   <pubDate>Thu, 15 Sep 2016 17:29:22 +0000</pubDate>
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   <title><![CDATA[Xpedition : Export Parts - Configuring Assigning Layers]]></title>
   <link>https://www.PCBLibraries.com/forum/export-parts-configuring-assigning-layers_topic1959_post8052.html#8052</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=2836">AP-EXAD</a><br /><strong>Subject:</strong> Export Parts - Configuring Assigning Layers<br /><strong>Posted:</strong> 14 Sep 2016 at 3:04am<br /><br /><div>I am using PCB Library Expert V2016.10<br><br>Are there any possibility to configure assigning PCB Library layers to Expedition layers?<br></div><div><br></div><div>i.e.:</div><ul><li>Component Outline will not be exported?</li><li>Terminal Outline will be exported to "User Draft Layer" </li></ul><div>Thank you<br>Andrej <br><br></div>]]>
   </description>
   <pubDate>Wed, 14 Sep 2016 03:04:43 +0000</pubDate>
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   <title><![CDATA[Xpedition : Encrypted ascii]]></title>
   <link>https://www.PCBLibraries.com/forum/encrypted-ascii_topic1829_post7502.html#7502</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=1">Nick B</a><br /><strong>Subject:</strong> Encrypted ascii<br /><strong>Posted:</strong> 08 Feb 2016 at 7:28am<br /><br /><div>Thanks for confirming!</div>]]>
   </description>
   <pubDate>Mon, 08 Feb 2016 07:28:15 +0000</pubDate>
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   <title><![CDATA[Xpedition : Encrypted ascii]]></title>
   <link>https://www.PCBLibraries.com/forum/encrypted-ascii_topic1829_post7501.html#7501</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=644">magnus.lictor</a><br /><strong>Subject:</strong> Encrypted ascii<br /><strong>Posted:</strong> 08 Feb 2016 at 6:22am<br /><br />The "EncryptData.exe" isn't there.&nbsp; I have downloaded the 2015.21 again, now it is there and everything is working.<br><br><br>Thanks<br>]]>
   </description>
   <pubDate>Mon, 08 Feb 2016 06:22:47 +0000</pubDate>
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   <title><![CDATA[Xpedition : Encrypted ascii]]></title>
   <link>https://www.PCBLibraries.com/forum/encrypted-ascii_topic1829_post7495.html#7495</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=1">Nick B</a><br /><strong>Subject:</strong> Encrypted ascii<br /><strong>Posted:</strong> 05 Feb 2016 at 7:26am<br /><br /><div>Can you please confirm that you have the "EncryptData.exe" file in the program directory? The default program directory for the Lite is</div><div><b>C:\Program Files (x86)\PCB Libraries\Library Expert 2015 Lite</b></div><div><br></div><div>If not, please download the latest 2015.21 build (the initial one didn't have this file) and try again.</div><div><br></div><div>Regards,<br>Nick</div><div><br></div>]]>
   </description>
   <pubDate>Fri, 05 Feb 2016 07:26:29 +0000</pubDate>
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   <title><![CDATA[Xpedition : Encrypted ascii]]></title>
   <link>https://www.PCBLibraries.com/forum/encrypted-ascii_topic1829_post7493.html#7493</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=644">magnus.lictor</a><br /><strong>Subject:</strong> Encrypted ascii<br /><strong>Posted:</strong> 05 Feb 2016 at 7:00am<br /><br />I am evaluating Library Ezpert Lite, version 2015-21.<br><br>When I add all the data for a cell, I want to create the "Encrypted Ascii" file.&nbsp; I click the "Build Part"<br>button and the "create footprint" window opens up.<br><br>I select the Expedition Translator, set the ouput format to "Encrypted Ascii, select an output directory&nbsp; and click on the "create" button.<br>Now a <b>NOT encrypted ascii file</b> is generated, and after this a window opens up:<br><br><b>"No executable file found".<br><br><br></b>As we are using VX, I cannot add non-encrypted file to the library<b>.<br><br><br></b>regards, Magnus<b><br></b><br><br><br>]]>
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   <pubDate>Fri, 05 Feb 2016 07:00:21 +0000</pubDate>
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