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  <title>PCB Libraries Forum : SON / QFN Calculations</title>
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  <pubDate>Mon, 13 Apr 2026 11:22:18 +0000</pubDate>
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   <title><![CDATA[SON / QFN Calculations : Ooops! I just noticed that the...]]></title>
   <link>https://www.PCBLibraries.com/forum/son-qfn-calculations_topic889_post3260.html#3260</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=2644">jnelso09</a><br /><strong>Subject:</strong> 889<br /><strong>Posted:</strong> 15 Mar 2013 at 1:34pm<br /><br />Ooops!&nbsp; I just noticed that the previously posted pic shows exactly the opposite of what I'm talking about - The center land is minimized and the outer lands are maximized.&nbsp; Same idea though - just switch the center pad to maximum tolerance and trim the outer lands.]]>
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   <pubDate>Fri, 15 Mar 2013 13:34:05 +0000</pubDate>
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   <title><![CDATA[SON / QFN Calculations : This might also help to clarify...]]></title>
   <link>https://www.PCBLibraries.com/forum/son-qfn-calculations_topic889_post3259.html#3259</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=2644">jnelso09</a><br /><strong>Subject:</strong> 889<br /><strong>Posted:</strong> 15 Mar 2013 at 1:31pm<br /><br />This might also help to clarify . . .<DIV>&nbsp;</DIV><DIV><img src="http://www.pcblibraries.com/forum/uploads/2644/QFNdesign.jpg" height="393" width="520" border="0" /></DIV>]]>
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   <pubDate>Fri, 15 Mar 2013 13:31:37 +0000</pubDate>
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   <title><![CDATA[SON / QFN Calculations : Our experience has been that vendor...]]></title>
   <link>https://www.PCBLibraries.com/forum/son-qfn-calculations_topic889_post3258.html#3258</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=2644">jnelso09</a><br /><strong>Subject:</strong> 889<br /><strong>Posted:</strong> 15 Mar 2013 at 12:47pm<br /><br /><P>Our experience has been that vendor recommended footprints for QFN devices either don't exist or they are contrary to applications&nbsp;for high-reliability hardware.&nbsp; For instance, we have found several vendors that recommend a solder mask defined center pad.&nbsp; We have found that when the center pad is completely surrounded by solder mask voiding in the solder joint increases and the ability to clean flux residues out from under these parts is difficult if not impossible.&nbsp; Of course this is coming from the high-rel mentality so commercial users would not be exposed to or even care about&nbsp;these issues.&nbsp; Below is a micro-section of a typical SON device that failed test for certain RF performance characteristics.&nbsp; We were never able to conclude the root cause but it was believed to be due to center pad voiding and/or flux trapped around the perimeter of the center pad.</P><DIV><SPAN style="FONT-FAMILY: 'Times New Roman','serif'; COLOR: #1f497d; FONT-SIZE: 10pt; mso-fareast-font-family: 'Times New Roman'; mso-ansi-: EN-US; mso-fareast-: EN-US; mso-bidi-: AR-SA"><?: prefix = v ns = "urn:schemas-microsoft-com:vml" /><v:shape id=_x0000_t75 stroked="f" filled="f" path="m@4@5l@4@11@9@11@9@5xe" o:preferrelative="t" o:spt="75" coordsize="21600,21600">&nbsp;<img src="http://www.pcblibraries.com/forum/uploads/2644/QFN-A.jpg" height="678" width="897" border="0" /></v:shape></SPAN></DIV>]]>
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   <pubDate>Fri, 15 Mar 2013 12:47:36 +0000</pubDate>
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   <title><![CDATA[SON / QFN Calculations : My suggestion is to use the component...]]></title>
   <link>https://www.PCBLibraries.com/forum/son-qfn-calculations_topic889_post3253.html#3253</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 889<br /><strong>Posted:</strong> 15 Mar 2013 at 7:16am<br /><br />My suggestion is to use the component mfr. recommended thermal pad size using the "Footprint Tab". <div>&nbsp;</div><div>The mfr. does testing for thermal cycle, shock and vibration on their recommended patterns and I've come to trust them, as I've never had a problem yet when I follow their recommendations. </div><div>&nbsp;</div>]]>
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   <pubDate>Fri, 15 Mar 2013 07:16:02 +0000</pubDate>
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   <title><![CDATA[SON / QFN Calculations : The algorithm for calculating...]]></title>
   <link>https://www.PCBLibraries.com/forum/son-qfn-calculations_topic889_post3250.html#3250</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=2644">jnelso09</a><br /><strong>Subject:</strong> 889<br /><strong>Posted:</strong> 15 Mar 2013 at 5:55am<br /><br />The algorithm for calculating the center (thermal)&nbsp;land dimensions for QFN/SON is fundamentally flawed.&nbsp; Why?&nbsp; Because it assumes maximum tolerance dimensions for the center&nbsp;land and then trims the inside of the peripheral lands to achieve the desired gap around the center pad.&nbsp; This will almost always create a land pattern that is non-symmetric with respect to the component pads.&nbsp; Because&nbsp;QFN's are fabricated&nbsp;from&nbsp;sheet copper in an array, the tolerance of the pads vary uniformly (for the most part) with respect to the etch process.&nbsp; This means that if the center pad is over-etched then&nbsp;the outer pads are also over-etched.&nbsp; And if the center pad is under-etched then so are the outer pads.&nbsp; Furthermore, the component peripheral&nbsp;pad&nbsp;length is also dictated by a saw or punch tolerance which has nothing to do with the etch tolerance and therefore should be considered independently AFTER the etch tolerances&nbsp;are accounted for.&nbsp; This is why is makes more sense to apply a uniform 'trimming' to both the center&nbsp;land and the inside of the peripheral lands - it maintains symmetry with the component&nbsp;fabrication etch process.&nbsp; <img src="http://www.pcblibraries.com/forum/smileys/smiley3.gif" height="17" width="17" border="0" alt="Shocked" title="Shocked" />&nbsp; <div>&nbsp;</div><div>My suggestion is to change the algorithm to calculate the center&nbsp;land dimensions based upon the nominal centerline of the gap around the component center pad.&nbsp;&nbsp;To calculate the center land dimensions use the nominal values for:&nbsp; Component package width (A), Thermal pad width (Wt), Peripheral land length (T), Pullback (PB), and center pad gap (g).&nbsp; The center land dimension equals (A+Wt)/2 - T - PB - g.&nbsp; If this number is larger than the maximum tolerance value of the&nbsp;center pad (Wtmax) then use Wtmax instead.&nbsp; </div><div>&nbsp;</div><div>For a detailed discussion of this topic please reference my whitepaper:</div><p style="margin: 0in 0in 0pt; text-align: center;" align="center"><b style="mso-bidi-font-weight: normal;"><span style="font-size: 14pt;"><font face="Times New Roman"><font size="1"><u></u></font></font></span></b></p><b style="mso-bidi-font-weight: normal;"><font face="Times New Roman"><font size="1"><u><div>&nbsp;</div><div align="center"><a href="http://smta.org/knowledge/journal_detail.cfm?ARTICLE_ID=208" target="_blank" rel="nofollow">BOTTOM TERMINATION COMPONENT LAND PATTERN DESIGN AND ASSEMBLY</a></div><a href="http://smta.org/knowledge/journal_detail.cfm?ARTICLE_ID=208" target="_blank" rel="nofollow"></a><div align="center"><a href="http://smta.org/knowledge/journal_detail.cfm?ARTICLE_ID=208" target="_blank" rel="nofollow">FOR HIGH RELIABILITY ELECTRONIC SYSTEMS</a></div><div align="center"><?: prefix = o ns = "urn:schemas-microsoft-com:office:office" /><o:p></o:p></div></u><div align="center"></div></font><div align="center"></div></font><div align="center"></div></b><div align="center">&nbsp;</div>This whitepaper&nbsp;is located on&nbsp;SMTA's website.<div></div><div></div><div></div>]]>
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   <pubDate>Fri, 15 Mar 2013 05:55:36 +0000</pubDate>
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