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  <title>PCB Libraries Forum : Standard Chip Package Case Codes &amp; Dimensions</title>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : IPC-7351B contains the 3-Tier...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post12145.html#12145</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 07 Feb 2022 at 10:01am<br /><br />IPC-7351B contains the 3-Tier Density Levels for Land Patterns.&nbsp;<div><br></div><div>However, that document is 12 years old and out of date and it took information from the 1987 IPC-SM-782 which is obsolete.</div><div><br></div><div>The solder Joint values are way too robust for today's technology.&nbsp;</div><div><br></div><div>Footprint Expert solder joint goals are derived from IPC J-STD-001 standard as it's the main standard that all other standards are built upon.&nbsp;</div><div><br></div>]]>
   </description>
   <pubDate>Mon, 07 Feb 2022 10:01:57 +0000</pubDate>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : Hi Tom,Please excuse me if you&amp;#039;ve...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post12144.html#12144</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=16797">AnonAnon</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 07 Feb 2022 at 5:41am<br /><br /><div>Hi Tom,</div><div><br></div><div>Please excuse me if you've answered this a thousand times but I'm looking to find which standard defined the "Least" and "Most" limits for each footprint. I can see IPC-SM-782 defines the nominal and references equations in a section 3.3? I am happy to purchase the standard but wanted to ensure it contained the correct information before I purchase.<br></div><div><br></div><div>Do the IPC standards only provide the nominal and one has to calculate the limits?</div><div><br></div><div>Kind regards,</div><div><br></div><div>David<br></div>]]>
   </description>
   <pubDate>Mon, 07 Feb 2022 05:41:55 +0000</pubDate>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : Read the User Guide in the main...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post11872.html#11872</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 08 Sep 2021 at 8:32am<br /><br />Read the User Guide in the main installation folder under "<b>Documents</b>".&nbsp;<div><br></div><div><ul style="margin-top:0in" ="disc"=""> <li ="msolistparagraph"="" style="margin-left:0in;mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:&quot;Times New Roman&quot;">Charter 1 Footprint     Expert Console Options<o:p></o:p></span></li> <li ="msolistparagraph"="" style="margin-left:0in;mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:&quot;Times New Roman&quot;">Charter 2 Footprint     Expert Calculator Options - Pad Stack Rules<o:p></o:p></span></li> <li ="msolistparagraph"="" style="margin-left:0in;mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:&quot;Times New Roman&quot;">Charter 3 Footprint     Expert Calculator Options – Drafting<o:p></o:p></span></li> <li ="msolistparagraph"="" style="margin-left:0in;mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:&quot;Times New Roman&quot;">Charter 4 Footprint     Expert Calculator Options – Fiducials<o:p></o:p></span></li> <li ="msolistparagraph"="" style="margin-left:0in;mso-list:l0 level1 lfo1"><span style="mso-fareast-font-family:&quot;Times New Roman&quot;">Charter 5 Footprint     Expert Toolbar Icons and Menu Options<o:p></o:p></span></li></ul>You cannot edit the program Master Options. You need to create your personal option files (as many as you want).&nbsp;</div><div><br></div><div>Select <b>File &gt; Save As &gt; Your Master Options .opt</b></div><div><br></div>]]>
   </description>
   <pubDate>Wed, 08 Sep 2021 08:32:13 +0000</pubDate>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : Hi Tom,For my Enterprise Edition...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post11871.html#11871</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=15164">phil.holden</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 08 Sep 2021 at 5:26am<br /><br />Hi Tom,<div><br></div><div>For my Enterprise Edition CLOUD Licensed the options under Pad Stack Rules are 'greyed' out. Does this mean that i am unable to control this globally?&nbsp;<img src="uploads/15164/Capture_2021-09-08_05-25-41.PNG" height="599" width="702" border="0" /></div>]]>
   </description>
   <pubDate>Wed, 08 Sep 2021 05:26:10 +0000</pubDate>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : To get 3 or more passive packages...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post11864.html#11864</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 07 Sep 2021 at 9:08am<br /><br /><div>To get 3 or more passive packages to fit into the same Footprint, find parts with the same dimensions and tolerances. If the package dimensions are the same but the tolerances are different, then round the tolerances off so that they are all the same.&nbsp;</div><div><br></div>Rounded Rectangle Pad Shape: You should change your Maximum Radius from 0.25 to 0.15 or 0.10 or something smaller.&nbsp;<div><br></div><div>Change this setting in "<b>Tools &gt; Options &gt; Pad Stack Rules &gt; SMD Corner Rounding &gt; Corner Radius Limit</b>".&nbsp;</div>]]>
   </description>
   <pubDate>Tue, 07 Sep 2021 09:08:55 +0000</pubDate>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : As is common procedure, especially...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post11863.html#11863</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=15164">phil.holden</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 07 Sep 2021 at 4:08am<br /><br />As is common procedure, especially during these times with supply-chain issues. We try and specify x3 MPNs for all of our passive devices.&nbsp;<div><br></div><div>As there could be 3 substituted parts fitted all with differing terminal lengths. How am i best addressing this when creating a passive library?&nbsp;</div><div><br></div><div>This is much less of a problem for active parts and connectors that are less 'interchangeable'.&nbsp;</div><div><br></div><div>Thanks</div><div><br></div><div>In addition to the above. I have noticed that the terminals sometimes overhang the pads when using 'rounded rectangle'. In your opinion, would this be a problem?&nbsp;</div><div><br></div><div><img src="uploads/15164/Capture.PNG" height="491" width="1000" border="0" /></div>]]>
   </description>
   <pubDate>Tue, 07 Sep 2021 04:08:23 +0000</pubDate>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : You need to attach a link to a...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post11742.html#11742</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 02 Jul 2021 at 8:47am<br /><br />You need to attach a link to a PDF file zipped or a URL link to the datasheet would be better.&nbsp;<div><br></div><div>Then we can post the Proteus footprint.&nbsp;</div><div><br></div><div>Are you using the Free <b>V2021 Footprint Expert Pro</b> for Proteus? You could create the footprint in a couple minutes.&nbsp;</div><div><br></div>]]>
   </description>
   <pubDate>Fri, 02 Jul 2021 08:47:52 +0000</pubDate>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : Hi,How to make a Proteus library...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post11740.html#11740</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=16237">lladam</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 02 Jul 2021 at 6:26am<br /><br />Hi,<div><br><div>How to make a Proteus library part of MEGA2560 Pro Mini, or where can find one please.</div><div><br></div><div>Because the board too small to put many pins on.</div><div><br></div><div>Thanks</div></div>]]>
   </description>
   <pubDate>Fri, 02 Jul 2021 06:26:24 +0000</pubDate>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : Use the mfr. recommended pattern...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post11375.html#11375</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 25 Mar 2021 at 11:59am<br /><br />Use the mfr. recommended pattern for this new upcoming component family.&nbsp;<div><br></div><div>Some manufacturers use a periphery solder joint goal and other use a Toe, Heel and Side pad stack.&nbsp;</div><div><br></div><div>This is a new Terminal Lead form that has not been fully tested by the world standards like IPC-J-STD-001 for solder joint acceptability.&nbsp;</div><div><br></div>]]>
   </description>
   <pubDate>Thu, 25 Mar 2021 11:59:13 +0000</pubDate>
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   <title><![CDATA[Standard Chip Package Case Codes &amp; Dimensions : Hi Tom,Thanks for the reply. Can...]]></title>
   <link>https://www.PCBLibraries.com/forum/standard-chip-package-case-codes-dimensions_topic2440_post11374.html#11374</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=15804">Arun7290</a><br /><strong>Subject:</strong> 2440<br /><strong>Posted:</strong> 25 Mar 2021 at 11:52am<br /><br />Hi Tom,<div><br><div>Thanks for the reply. Can we use the above listed package sizes for Wraparound parts as well in the same case code?&nbsp;</div><div><br></div><div>Because It is mentioned that the above case code dimensions are only for&nbsp;<span style=": rgb251, 251, 253;">Standard Chips.&nbsp;</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><span style=": rgb251, 251, 253;">And I am working on some wraparound packages of the standard case code.&nbsp;</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><span style=": rgb251, 251, 253;">Can we use PCB library expert for footprint creation for these parts?&nbsp;</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><span style=": rgb251, 251, 253;">Or Is it better to follow the Manufacturer recommended land pattern?</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><span style=": rgb251, 251, 253;"><img src="uploads/15804/q1.PNG" height="285" width="543" border="0" /><br></span></div></div>]]>
   </description>
   <pubDate>Thu, 25 Mar 2021 11:52:42 +0000</pubDate>
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