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Proportional Through-hole Padstacks
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zasanil View Drop Down
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Joined: 27 Feb 2012
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Points: 10 		Post Options Post Options   Thanks (0) Thanks(0)   Quote zasanil Quote  Post ReplyReply Direct Link To This Post Posted: 21 Mar 2012 at 9:56am
Thanks a bunch for sharing this great resource.
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kmoyer72 View Drop Down
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Points: 1 		Post Options Post Options   Thanks (0) Thanks(0)   Quote kmoyer72 Quote  Post ReplyReply Direct Link To This Post Posted: 21 Mar 2012 at 1:40pm
thanks
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Points: 37 		Post Options Post Options   Thanks (0) Thanks(0)   Quote konraditen Quote  Post ReplyReply Direct Link To This Post Posted: 26 Mar 2012 at 5:25pm
Appreciate the work that was put in.
Thank you.

K
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Points: 1 		Post Options Post Options   Thanks (0) Thanks(0)   Quote Nellie44Militello Quote  Post ReplyReply Direct Link To This Post Posted: 01 Aug 2012 at 1:01pm
Originally posted by Nick B Nick B wrote:

Here is the latest Through-hole Padstacks file -
 
 
 
I was just browsing for relevant posts for my small volume pcb assembly project and I happened to stumble upon yours. thanks for this useful link. it's appreciated.
 
dave
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budnoel View Drop Down
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Points: 17 		Post Options Post Options   Thanks (0) Thanks(0)   Quote budnoel Quote  Post ReplyReply Direct Link To This Post Posted: 02 Aug 2012 at 10:07am

There doesn't appear to be any differentiation regarding density level in this new chart.  Am I missing something?
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Tom H View Drop Down
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Points: 5718 		Post Options Post Options   Thanks (1) Thanks(1)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 02 Aug 2012 at 10:35am
The IPC-7251 for through-hole component package land pattern footprints has not been released yet.
 
I really don't know why IPC is taking so long.
 
PCB Libraries, Inc. developed the Proportional Through-hole Padstack Chart which takes into consideration all 3-Tiers in a single solution.
 
Small hole sizes use the Least Environment for the annular ring. Average hole sizes use the Nominal Environment annular ring and larger hole sizes use the Most Enviroment annular ring.
 
Where as IPC-7251 uses the same annular ring for each environment regardless of how big the hole size is.
 
Example: The IPC-7251 annular ring for Nominal Environment is 10 mil (0.25 mm) regardless if the hole size is 30 mil (0.76 mm) or 98 mil (2.5 mm). The proportional padstack uses a 10 mil (0.25 mm) annular ring for 30 mil (0.76 mm) hole, but the 98 mil (2.5 mm) hole has a 25 mil (0.635 mm) annular ring.
 
PCB Libraries, Inc. position is that large holes require large annular rings for more solder but also to control heat dissipation.
 
So the Proportional Padstack Chart meets or beats IPC-7251 standards.
 
We will release the through-hole component families on August 11 and the user will be able to select from IPC-7251 3-Tier or use the Proportional padstack (which is the PCB Footprint Expert) default.
 
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hawesa View Drop Down
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Points: 2 		Post Options Post Options   Thanks (0) Thanks(0)   Quote hawesa Quote  Post ReplyReply Direct Link To This Post Posted: 21 Aug 2012 at 7:55am
Hi all,
 
Could you explain how the VIA padstack dimensions are calculated in the padstack chart?
They appear to follow a different formula to the PTH component Padtacks, unless I'm missing something!
e.g. a Level B padstack with a FHS of 0.4mm has a pad size of 1.00mm whilst in the VIA chart, a 0.4mm hole has a pad size of between 0.65mm and 0.8mm.
I realise there is no solder fillet required on a via but have been tearing what little there is left of my hair out trying to figure out how the VIA pad is calculated and if it is defined anywhere in IPC!Confused
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Tom H View Drop Down
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Points: 5718 		Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 21 Aug 2012 at 8:20am
Vias are not specified in any IPC standard.
 
A through-hole that needs to support a component lead is totally different than a hole that does not ever have a component lead in it.
 
A through-hole via simply needs to conduct current.
 
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hawesa View Drop Down
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I am trying to define a set of standard or default vias to be used by the layout team here and was intending to use the chart as a starting point but I need to understand how the values are calculated. We do not allow any breakout (worst case tangency) so how do we ensure the default vias provide for this?
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Points: 576 		Post Options Post Options   Thanks (0) Thanks(0)   Quote jameshead Quote  Post ReplyReply Direct Link To This Post Posted: 21 Aug 2012 at 8:43am
I've brought this up before with Tom.  Like Hawesa, I've always used the standard IPC calculations for vias as well, as have a number of designers I've worked with, but then again I've also worked with a handful of designers who've thought the same as Tom.

I tried to clarify it with the IPC and got the answer back that the standard does cover vias as well as through-hole pads but other IPC people I've spoken to have thought the opposite.  I think it certainly needs some clarification.  I don't know if the IPC have looked at this recently and revised it?

Currently I'm sticking with the IPC calculations for vias just for consistancy but I'd be perfectly happy to use the PCB Libraries padstacks for vias if the IPC updated the standard.
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