Dear all,

We recently switched our CAD tool to Altium and are currently setting up a new parts library.

Our first thought was using the Altium IPC wizard for creating the footprints but it does not operate as expected. Looking for an alternative, I found the Library Expert tool which seems to do the job quite nicely. The current method I am testing is downloading the footprints from the POD database and then exporting them with the POD version of the tool.

I am currently testing the effect of the different settings in the Drafting tab and there are some things that I cannot make sense of:

- Setting the "Pin 1 Dot Size (not-to-exceed)" value to 0.00 removes the Pin 1 dot from the assembly outline for SOFL, SOIC and SOP packages but not for packages of "Used defined package" type

- Enabling the "Autogenerate Pin 1 Indicator Line" works for the packages mentioned above but has no effect for BGAs. In another post I read that the new way of marking pin 1 of BGA packages is leaving out the silk screen at that position. Is there a way to automatically do this?

- The default value for "Include Polarity Indicators" is off. I would expect that the polarity is absolutely necessary for the EMS to assemble the parts. If not from the assembly layer, where would the EMS get the orientation information from?

- Turning this option on creates a chamfered corner at pin 1. The library includes a SOP8 package which already has an dot on the assembly layer to indicate pin 1, regardless of this option. This seems to be the only package type (currently in the library) with this effect.

- When enabling the "Expand Courtyard to Include Legend" option, I would expect that the courtyard would extend to include the polarity marker (if generated) but it seems to have no effect.

As you can see, my expectations differ from the actual behaviour at some points. Can you tell me, which is correct? :D

One final question is related to modifying downloaded parts. The current library contains a part of component type "User defined package" which has been created according to the datasheet but where the manufacturer released an application note with a recommendation to increase the pad size. With the POD version of LE, it seem that I cannot change the padstack and then export the component with increased pad sizes, is this correct?

Best regards and thank you very much in advance,

Jelle

http://www.pcblibraries.com/products/fpx/userguide/default.asp?ch=9.3" rel="nofollow - http://www.pcblibraries.com/products/fpx/userguide/default.asp?ch=9.3  

But the only way to automate this process is to use the "Library Expert Enterprise" so you can save all your work back to FPX file. 

We're going to start Leasing "Library Expert Enterprise" next week for the price of yearly maintenance (20% of the list price to purchase). 

Inserting your own Polarity Markers gives you 100% flexibility. Large parts get large marking small parts get small marking. You control the Size, Location, Shape, Layer, Filled or Unfilled. 

Here are the various shapes you can use - 

Trying to automate Polarity Marking is complex. 

The Placement Courtyard is defined by rules in the IPC-7351 guideline. The 7351 does not have any guidelines for Polarity Marking. 

All FP Designer parts for non-standard parts and connectors, we add the Polarity Marking to all of those parts for you. It's easy to do and only takes a minute once you master the technique.