How is a courtyard excess defined?

However, IPC has not updated their guidance on this land pattern feature in over 12 years. Especially for microminiature packages and high-density PCB design layouts. 

We adopted IPC-7351 for both the mathematical model for pad stack and courtyard calculations, but a lot has changed in the past 12 years. 

One of the changes should be the elimination of Fabrication and Assembly Tolerances in the mathematical model. Also, updating and changing all negative solder joint goals to 0.00 as the negative values were applied to compensate for the robust Fabrication and Assembly Tolerances. 

The placement courtyard is also evolving and becoming smaller due to assembly placement accuracy. But the courtyard excess is also used for component rework area to allow room for extraction tools, cleaning and replacing defective components. 

The question should be "I'm designing a PCB prototype and is there a requirement for rework?" If not, you can reduce the placement courtyard size. If you do plan on rework, then the package height is a big concern as rework tools need space to extract the component. 

The last IPC-7351B released in 2010 defines the 3-Tier courtyard sizes for Least 0.10, Nominal, 0.25 and Most 0.50. But we found that the nominal density can easily handle a 0.20 courtyard excess and Most density a 0.40 courtyard excess. These have been the default values in Footprint Expert for several years now with no one complaining. 

The part placement should allow the courtyard outline to bump up against each other and not overlap.