PCB Libraries Forum Homepage
Forum Home Forum Home > PCB Footprint Expert > Questions & Answers
  New Posts New Posts RSS Feed - PQFN/PSON Footprint Name
  FAQ FAQ  Forum Search   Events   Register Register  Login Login

PQFN/PSON Footprint Name

 Post Reply Post Reply
Author
Message
JZsori View Drop Down
Advanced User
Advanced User


Joined: 01 Mar 2012
Status: Offline
Points: 65
Post Options Post Options   Thanks (0) Thanks(0)   Quote JZsori Quote  Post ReplyReply Direct Link To This Post Topic: PQFN/PSON Footprint Name
    Posted: 01 Jun 2012 at 7:05pm
There are multiple instances with the same name and description (PSON50P400X400X80-14, for example) but one has rectangular pads and the other has D-Shape pads.  There should be some way to differentiate.
Back to Top
Back to Top
Tom H View Drop Down
Admin Group
Admin Group
Avatar

Joined: 05 Jan 2012
Location: San Diego, CA
Status: Offline
Points: 5716
Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 22 Oct 2012 at 10:39am

The Component Lead Shape and the resulting Pad Shape have nothing to do with the footprint pattern name.

Here is a component manufacturer that produces QFN packages with D-shape Package Leads -

 
Here is their recommended footprint with Rectangular footprint pads. Also notice that the Component Thermal Tab has a Chamfer Corner by Pin 1 and rounded corners on the others, but the manufacturer recommends a solid square with no chamfer or rounded corners. So it's really a "User Option".

             

Also note that the manufacturer is calling the footprint a "Land Pattern" and they are using the IPC-7351 Land Pattern Naming Convention with the JEDEC variation in the Land Pattern Name (W6) to discriminate the Thermal Pad size.
 
Back to Top
Sanand View Drop Down
New User
New User
Avatar

Joined: 27 Oct 2012
Location: California
Status: Offline
Points: 1
Post Options Post Options   Thanks (0) Thanks(0)   Quote Sanand Quote  Post ReplyReply Direct Link To This Post Posted: 27 Oct 2012 at 2:01am
Hi,
 
I am new user for this site. I have some questions regarding the land pattern and wonder if this forum is suit for it.
 
Do you know of any minimum clearance along the edge of PCB or memory module must be? Is it 0.050" to be minimum or 0.150"?
 
And minimum gap between to components footprint or between two terminals of passive 0201?
 
Thanks
 
Back to Top
Tom H View Drop Down
Admin Group
Admin Group
Avatar

Joined: 05 Jan 2012
Location: San Diego, CA
Status: Offline
Points: 5716
Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 27 Oct 2012 at 8:02am
The minimum board edge to any feature - component, via, trace, copper pour is 40 mils (1.0 mm).
 
The minimum SMT component to component body or component pad to component pad gap is 10 mil (0.25 mm) for different components.
 
The minumum pad to pad gap on the same component is 6 mils (0.15 mm).
 
The minimum pad to thermal pad gap on the same component is 8 mils (0.20 mm).
 
You can also get more information by reading my blog here -
 
Copy/Paste the entire Blog into a Word document or print it out to PDF. We don't know how long Mentor Graphics will keep it available.
 
Back to Top
rdl86626 View Drop Down
Advanced User
Advanced User
Avatar

Joined: 20 Jul 2012
Location: Hollister, CA
Status: Offline
Points: 83
Post Options Post Options   Thanks (0) Thanks(0)   Quote rdl86626 Quote  Post ReplyReply Direct Link To This Post Posted: 29 Oct 2012 at 8:35am

Tom,

 

I was reading the form where you statedThe minimum board edge to any feature - component, via, trace, copper pour is 40 mils (1.0 mm)”. I have a hard time with IPC spec’s and where to find out things like that.
 
I have been using .040 for planes and .020 for traces. What spec are these things in?
 
I don't mean to sound stupid,
 
Dumb Rick
 
Back to Top
Tom H View Drop Down
Admin Group
Admin Group
Avatar

Joined: 05 Jan 2012
Location: San Diego, CA
Status: Offline
Points: 5716
Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 29 Oct 2012 at 8:55am
I don't get all of the rules from IPC, but they do document a lot of DFM stuff in the IPC-2221 and IPC-2222.
 
I use fabrication shops and common sense most of the time.
 
Example: I went to Google and typed "DFM Guidelines" and I found this PDF file -
 
This document produced in Hawaii surveyed several California Fabrication shops -
  • TTM
  • Velie Circuits
  • Multek
  • Dynamic Details
  • Via Systems
  • Fine Pitch

There are comparisons between manufacturers.

You say to pull your planes back 40 mils but traces 20 mils. To me this means that you have traces without a reference plane below them. I wouldn't do that.
 
The main reasons why features need to be pulled back from the board edge is the answer to your question. Is it because the fabrication shop is V-scoring or using a router. When breaking up the panel into individual boards, V-Scoreing can leave rough edges that need to be panelerized plus the process requires recessed features as not to damage them.
 
Does your panel need to remain intact for assembly? If so, there will be breakaway rat-bite holes in the router process.
 
Back to Top
rdl86626 View Drop Down
Advanced User
Advanced User
Avatar

Joined: 20 Jul 2012
Location: Hollister, CA
Status: Offline
Points: 83
Post Options Post Options   Thanks (0) Thanks(0)   Quote rdl86626 Quote  Post ReplyReply Direct Link To This Post Posted: 29 Oct 2012 at 9:07am
Thanks Tom,
 

   Thank you very much and I see your point. We have boards that are ridgid flex with analog /digial mixed. I have 1 or 2 traces that break that rule, which I do break if I have to, like you say common sense is the best rule.

Thanks again.

not so dumb Rick

 
 
Back to Top
 Post Reply Post Reply

Forum Jump Forum Permissions View Drop Down



This page was generated in 0.156 seconds.