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PCB Design Optimization Starts in the CAD Library
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Nick B View Drop Down
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Joined: 02 Jan 2012
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Points: 1909 		Post Options Post Options   Thanks (28) Thanks(28)   Quote Nick B Quote  Post ReplyReply Direct Link To This Post Topic: PCB Design Optimization Starts in the CAD Library
    Posted: 20 Jul 2012 at 9:32am
PCB Design Optimization (updated September 5, 2013)
This 149-page Presentation is absolutely FREE!
 
Just make sure you are logged in to the forum and click this link:
  PCB Design Optimization Presentation
 
(first 25 slides of the 146-slide presentation are shown below)


The following document represents every Surface Mount component family in the PCB Library Expert with graphic illustrations of every 3D STEP model, example Footprint with Silkscreen and updated Solder Joint Goal Tables:

The Library Expert's Surface Mount Component Families
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konraditen View Drop Down
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Joined: 26 Mar 2012
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Points: 37 		Post Options Post Options   Thanks (4) Thanks(4)   Quote konraditen Quote  Post ReplyReply Direct Link To This Post Posted: 20 Jul 2012 at 10:52am
thanks for the share.

Konrad
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Nick B View Drop Down
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Points: 1909 		Post Options Post Options   Thanks (3) Thanks(3)   Quote Nick B Quote  Post ReplyReply Direct Link To This Post Posted: 20 Jul 2012 at 11:08am
No problem at all!

Feel free to click    Thanks    for posts you like - keeps the forum cleaner. It also gets forum users more points.  Smile
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Nick B View Drop Down
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Points: 1909 		Post Options Post Options   Thanks (4) Thanks(4)   Quote Nick B Quote  Post ReplyReply Direct Link To This Post Posted: 13 Oct 2012 at 7:32pm
This presentation has been updated!!
Just make sure you are logged in to the forum and click this link (same as the link above):
PCB Design Optimization Presentation
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tinghai899220 View Drop Down
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Points: 1 		Post Options Post Options   Thanks (0) Thanks(0)   Quote tinghai899220 Quote  Post ReplyReply Direct Link To This Post Posted: 30 Oct 2012 at 4:38am
thanks
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Points: 8 		Post Options Post Options   Thanks (0) Thanks(0)   Quote Blueprint Quote  Post ReplyReply Direct Link To This Post Posted: 07 Jan 2013 at 5:21pm
Thanks !
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Points: 1 		Post Options Post Options   Thanks (0) Thanks(0)   Quote ijossa Quote  Post ReplyReply Direct Link To This Post Posted: 13 Feb 2013 at 9:54am
Thanks! Very good overview!
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Points: 1 		Post Options Post Options   Thanks (0) Thanks(0)   Quote rushway Quote  Post ReplyReply Direct Link To This Post Posted: 26 Mar 2013 at 8:37pm

Great! This is one of the most excellent document I have read.
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Points: 17 		Post Options Post Options   Thanks (0) Thanks(0)   Quote budnoel Quote  Post ReplyReply Direct Link To This Post Posted: 17 Jun 2013 at 5:36am
Hello - We have been creating our standard library component padstacks with a one-to-one relationship between the pad size and the Soldermask size.  On our fabrication drawing we then include the following note: "RESIZING FOR OPTIMAL MASK CLEARANCE TO CONDUCTIVE FEATURES PERMISSIBLE."  Is this the best approach or should we be internally adjusting our SM to Pad clearances for each design before we release them for fabrication?
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Tom H View Drop Down
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Points: 5719 		Post Options Post Options   Thanks (0) Thanks(0)   Quote Tom H Quote  Post ReplyReply Direct Link To This Post Posted: 17 Jun 2013 at 6:30am
You're on the right track. When I tour manufacturing facilities and that question always comes up and the answer is always the same. Please provide all solder mask features 1:1 scale so we have a known starting point to swell the mask to fit your PCB trace/space technology and our fabrication tolerance.
 
"The Solder Mask provided in the Gerber data can be swelled to accomodate your manufacturing tolerances. Do not expose any traces, vias or copper pour."
 
There a many different ways to word this fabrication note, so I would discuss it with the fabrication shop to get their feedback.
 
I have noticed in many CAD tools that they provide a global solder mask swell for pad features, but if you do this, I would also notify fabrication what you did.
 
 
 
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