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  <pubDate>Fri, 24 Jul 2026 11:37:43 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Under-body outward L-lead courtyard calculation]]></title>
   <link>https://www.PCBLibraries.com/forum/underbody-outward-llead-courtyard-calculation_topic3663_post14599.html#14599</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=17440">felecro</a><br /><strong>Subject:</strong> Under-body outward L-lead courtyard calculation<br /><strong>Posted:</strong> 23 Jul 2026 at 1:03am<br /><br />Ok, thanks for the explanation.]]>
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   <pubDate>Thu, 23 Jul 2026 01:03:59 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Molded Body D1 Dimension]]></title>
   <link>https://www.PCBLibraries.com/forum/molded-body-d1-dimension_topic2261_post14598.html#14598</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Molded Body D1 Dimension<br /><strong>Posted:</strong> 22 Jul 2026 at 12:15pm<br /><br />The main issue with the Molded Body terminal lead flat against the package body is the 3D Model.&nbsp;<div><br></div><div>We'll add a new component family for the&nbsp;<span style=": rgb251, 251, 253;">EIA 7343 series but the 3D STEP model will be an Extruded Block (no terminal leads).&nbsp;</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><span style=": rgb251, 251, 253;">This condition will take place when 'D1' is less than 0.60 mm than 'D'. The program will throw a warning.&nbsp;</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><span style=": rgb251, 251, 253;">It will be in the next V26.08 pre-release next week.&nbsp;</span></div><div><span style=": rgb251, 251, 253;"><br></span></div><div><span style=": rgb251, 251, 253;">Thanks</span></div><div><span style=": rgb251, 251, 253;"><br></span></div>]]>
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   <pubDate>Wed, 22 Jul 2026 12:15:09 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Molded Body D1 Dimension]]></title>
   <link>https://www.PCBLibraries.com/forum/molded-body-d1-dimension_topic2261_post14597.html#14597</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Molded Body D1 Dimension<br /><strong>Posted:</strong> 22 Jul 2026 at 8:40am<br /><br />The Molded Body component family in the IPC-7351/7352 is intended for the JEDEC DO-241 (SMA, SMB &amp; SMC) where the terminal lead is 0.20 mm thick and requires 0.60 mm difference between the 'D' and 'D1' dimensions.&nbsp;<div><br></div><div><img src="uploads/3/Molded_Body_Resistor.png" height="359" width="696" border="0" /><br></div><div>&nbsp;</div><div>The&nbsp;<span style=": rgb251, 251, 253;">EIA 7343–31 has the terminal leads flat against the component package body.&nbsp;</span></div><div><br></div><div>Use FP Designer and the mfr. recommended pattern to create these footprints.&nbsp;</div><div><br></div><div><br></div>]]>
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   <pubDate>Wed, 22 Jul 2026 08:40:05 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Molded Body D1 Dimension]]></title>
   <link>https://www.PCBLibraries.com/forum/molded-body-d1-dimension_topic2261_post14596.html#14596</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=19408">AA310</a><br /><strong>Subject:</strong> Molded Body D1 Dimension<br /><strong>Posted:</strong> 22 Jul 2026 at 8:19am<br /><br />Hello hello,<div><br></div><div>I am running the 26.07 version and the expected D1 reduction for a D case tantalum cap (EIA 7343–31) is 0.6 mm which I find ridiculous. I've measured most capacitors that we use in our designs (since the datasheets do not mention this parameter) and their D1 is at a minimum 7 mm.<div><br></div><div>Is there any way around this? I would like the footprints to be as accurate as possible. Thank you for your support!</div></div>]]>
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   <pubDate>Wed, 22 Jul 2026 08:19:07 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Under-body outward L-lead courtyard calculation]]></title>
   <link>https://www.PCBLibraries.com/forum/underbody-outward-llead-courtyard-calculation_topic3663_post14595.html#14595</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> Under-body outward L-lead courtyard calculation<br /><strong>Posted:</strong> 21 Jul 2026 at 8:25am<br /><br />All component packages taller than 10 mm get a larger courtyard excess per IPC-7351B Table 3-20. This is to make rework easier for failed components. You need to get extraction equipment (like heat nozzles) to unsolder the leads and remove the nonfunctional component and replace a new one.&nbsp;<div><br></div><div>However, if there are no plans on reworking failed packages, then change the courtyard excess to 0.20 or whatever value is your default setting in '<b>Tools &gt; Options &gt; Terminals &gt;&nbsp;</b><span style=": rgb251, 251, 253;"><b>Under-body Outward L Lead &gt; Courtyard</b>'.</span></div><div><br></div>]]>
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   <pubDate>Tue, 21 Jul 2026 08:25:48 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Under-body outward L-lead courtyard calculation]]></title>
   <link>https://www.PCBLibraries.com/forum/underbody-outward-llead-courtyard-calculation_topic3663_post14594.html#14594</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=17440">felecro</a><br /><strong>Subject:</strong> Under-body outward L-lead courtyard calculation<br /><strong>Posted:</strong> 20 Jul 2026 at 11:19pm<br /><br />Hello,&nbsp;<br><br>Yesterday I was approaced by one of our designers who has an issue with a new aluminium capacitor we added to the Altium component database. He wanted to use the new capacitor as a replacement for another that was added to the DB a few years ago. He expected them to be interchangable because they have same dimensions, but he encountered an issue with clearance between components.&nbsp;<div><br></div><div>As it turns out, the new capacitor has bigger courtyard and the reason for this is different courtyard calculation setting in the newever versions of FP Expert. From what I can see, the 2026 and 2025 version both have it under&nbsp; "Under-body Outward L Lead" settings. If the component height is greater than 10mm, the nominal density courtyard expansion is 0.4mm. If it's below 10mm, the standard 0.2mm is used.&nbsp;&nbsp;<br><br>I was wondering what was the motivation for this change and when did it happen? I tried search the forum for this topic but couldn't find anything about it.&nbsp;</div>]]>
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   <pubDate>Mon, 20 Jul 2026 23:19:03 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : BGAs, Density Levels, and Courtyard Changes]]></title>
   <link>https://www.PCBLibraries.com/forum/bgas-density-levels-and-courtyard-changes_topic3661_post14590.html#14590</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=15623">mnperry</a><br /><strong>Subject:</strong> BGAs, Density Levels, and Courtyard Changes<br /><strong>Posted:</strong> 02 Jul 2026 at 8:42am<br /><br />Thank you Tom!]]>
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   <pubDate>Thu, 02 Jul 2026 08:42:35 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : BGAs, Density Levels, and Courtyard Changes]]></title>
   <link>https://www.PCBLibraries.com/forum/bgas-density-levels-and-courtyard-changes_topic3661_post14589.html#14589</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> BGAs, Density Levels, and Courtyard Changes<br /><strong>Posted:</strong> 02 Jul 2026 at 8:09am<br /><br />BGA's are One Tier Density Level.&nbsp;<div><br></div><div>Setup the BGA rules in 'Tools &gt; Options &gt; Terminals &gt; Collapsing BGA'</div><div><br></div><div>You define all the settings per Ball Diameter. You can also add additional ball diameters.</div><div><ul><li>Ball Diameter</li><li>Pad Size Reduction (Adj. +/-)</li><li>Tolerance (Pad Var +)</li><li>Pad Size Rounding</li><li>Solder Mask +/-</li><li>Paste Mask +/-</li><li>Courtyard Excess +</li></ul><div><img src="uploads/3/BGA_Opti&#111;ns_2026-07-02_08-06-39.png" height="542" width="736" border="0" /><br></div></div><div><br></div>]]>
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   <pubDate>Thu, 02 Jul 2026 08:09:10 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : BGAs, Density Levels, and Courtyard Changes]]></title>
   <link>https://www.PCBLibraries.com/forum/bgas-density-levels-and-courtyard-changes_topic3661_post14588.html#14588</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=15623">mnperry</a><br /><strong>Subject:</strong> BGAs, Density Levels, and Courtyard Changes<br /><strong>Posted:</strong> 02 Jul 2026 at 7:48am<br /><br />When I change density levels from "N" to "L" would I expect to see a change in Courtyard excess for BGA devices?<div><br></div><div>I see in Options\Terminals\SM Grid Array and BGA...that:<br><br>"Grid array settings are not subject to Density Level Rules.</div><div><br></div><div><br><div><br></div><div><br></div></div>]]>
   </description>
   <pubDate>Thu, 02 Jul 2026 07:48:49 +0000</pubDate>
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   <title><![CDATA[Questions &amp; Answers : Font settings]]></title>
   <link>https://www.PCBLibraries.com/forum/font-settings_topic3659_post14585.html#14585</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=201">Jeff.M</a><br /><strong>Subject:</strong> Font settings<br /><strong>Posted:</strong> 23 Jun 2026 at 9:13am<br /><br />Could you explain how would such an option would work, bearing in mind that the footprint is already formed when it gets to the translator?&nbsp; Sounds like it might need a cross-reference table.&nbsp; If it gets too complex, we should pursue it off the forum.<div>Jeff</div>]]>
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   <pubDate>Tue, 23 Jun 2026 09:13:51 +0000</pubDate>
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