PCB Libraries Forum : Generic Footprints for CAPC and RESC https://www.PCBLibraries.com/forum/ Mon, 20 Apr 2026 22:37:20 +0000 Thu, 07 May 2020 18:27:32 +0000 http://blogs.law.harvard.edu/tech/rss Web Wiz Forums 12.07 360 https://www.PCBLibraries.com/forum/RSS_post_feed.asp?TID=2628 <![CDATA[PCB Libraries Forum]]> https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif https://www.PCBLibraries.com/forum/ <![CDATA[Generic Footprints for CAPC and RESC : There are 3-tiers for the Rectangular...]]> https://www.PCBLibraries.com/forum/generic-footprints-for-capc-and-resc_topic2628_post10734.html#10734 Author: Tom H
Subject: 2628
Posted: 07 May 2020 at 6:27pm

There are 3-tiers for the Rectangular End Cap packages. 

The solder Joint Goal values are all user definable. 

IPC-7351 is now a Guideline and has a basic starting point. 

The smaller the package the slighter the solder joint goal variance. 

Here are the current Solder Joint Goal tables - uploads/3/Library_Expert_Solder_Joint_Goal_Tables.zip

Note: there are different solder joint goals for every Chip Package size. 

]]> Thu, 07 May 2020 18:27:32 +0000 https://www.PCBLibraries.com/forum/generic-footprints-for-capc-and-resc_topic2628_post10734.html#10734 <![CDATA[Generic Footprints for CAPC and RESC : Ok, once I have all of these tolerances...]]> https://www.PCBLibraries.com/forum/generic-footprints-for-capc-and-resc_topic2628_post10733.html#10733 Author: bfrantz04
Subject: 2628
Posted: 07 May 2020 at 5:47pm

Ok, once I have all of these tolerances put together how do I use these with the Solder Joint Goal Tables to calculate dimensions?  

Do we use maximal or least material or some combination of both?

Also it looks like the rules are the same for capacitors and resistors now?
]]> Thu, 07 May 2020 17:47:15 +0000 https://www.PCBLibraries.com/forum/generic-footprints-for-capc-and-resc_topic2628_post10733.html#10733 <![CDATA[Generic Footprints for CAPC and RESC : The package sizes are fairly stable....]]> https://www.PCBLibraries.com/forum/generic-footprints-for-capc-and-resc_topic2628_post10731.html#10731 Author: Tom H
Subject: 2628
Posted: 07 May 2020 at 12:50pm

The package sizes are fairly stable. It's the tolerances that are all over the map. 

Build your discrete library using the same package dimensions and tolerances. 

Different mfr.'s with have different package and terminal lead tolerances and these tolerances are used to create the pad stack length and width. 

Use reasonable tolerances that the majority of your suppliers use. Find common tolerances. 

]]> Thu, 07 May 2020 12:50:28 +0000 https://www.PCBLibraries.com/forum/generic-footprints-for-capc-and-resc_topic2628_post10731.html#10731 <![CDATA[Generic Footprints for CAPC and RESC : I would like to create generic...]]> https://www.PCBLibraries.com/forum/generic-footprints-for-capc-and-resc_topic2628_post10730.html#10730 Author: bfrantz04
Subject: 2628
Posted: 07 May 2020 at 12:42pm

I would like to create generic footprints for standard component sizes.  

For instance from EIA 0201 to 1210 for capacitors and EIA 0201 to 1210 for resistors.  

Having only a few verified footprints will help keep our library maintenance down to a manageable number.

Are variations between manufacturers consistent enough to do this?  

Do I just pick a representative manufacturer and go with that?


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