Hi,

The problem is that I initally have checked in my "Master Options" under Options > Drafting > Silkscreen Outlines and Text > All Density Levels  the box "Add Outline to Footprint" since I want by default a silkscreen in all my designs. But for smaller footprints ( ie. capacitors, resistors 0402, 0603) I don´t want the default silkscreen created. Why? Becayse the silkscreen is to small to be printed in the sides of the pads between the gap, and the tool generates a "C" form shape around the pads. For me it is a problem because if the routed signal in the top or bottom layer is a high speed signal the silkscreen could affect the signal integrity. So I want it deleted.

Therefore, I change it in the particular menu in the calculator unchecking this box and I update it pushing Calculate. In the Footprint dialog the footprint appears to be updated. I then proceed to Add to Library and when I open it from the library the Silkscreen is still there. It looks like the property for the silkscreen is being inherit even when I specifically tell it not to do so.

Can you please orientate me to check if there could be anything I am missing in the process?

Uncheck the box and you will not get silkscreen outlines on 0201, 0404 or any small package. 

Thanks!

It worked for the 0201, 0402 chips. But for example I had a component that is not a chip. A DFN Crystal, and after changing the property you mentioned the silkscreen outline dissapeared. Somehow the tool considered the silkscreen was too small but I want the silkscreen in that particular component to appear.

I tried the same I mentioned in my original post, I changed it in the particular menu in the calculator unchecking the box you mentioned and I updated it pushing "Calculate". Then the silkscreen appeared. I updated the library but somehow when I reload the footprint my changes disappear.

Is this normal behaviour?

There are 2 workarounds.