Product Suggestions - Component Placement Courtyards

Component Placement Courtyards

Printed From: PCB Libraries Forum
Category: PCB Footprint Expert
Forum Name: Product Suggestions
Forum Description: request new features
URL: https://www.PCBLibraries.com/forum/forum_posts.asp?TID=1905
Printed Date: 12 Oct 2024 at 9:17pm

Topic: Component Placement Courtyards

Posted By: Todd Manning
Subject: Component Placement Courtyards
Date Posted: 15 Jun 2016 at 8:40pm

Hello,

Is it possible to have a courtyard generated for component placement to ensure that components are not placed too close to one another for assembly and rework. Currently the component courtyard is created based on an "Courtyard Excess" value but I'm assuming it would probably have to be based on height. Does IPC have a standard for this that can be incorporated into the software?

Thanks
Todd

Replies:

Posted By: Tom H
Date Posted: 16 Jun 2016 at 7:27am

The current IPC Courtyards have been around since 1987 when IPC-SM-782 was released and introduced them. They are currently a fixed value for each Density Level.

0.12 Excess for Least
0.25 Excess for Nominal
0.50 Excess for Most

We are discussing with IPC to introduce a new style of Courtyard Excess so that when the courtyard is next to a component body it's one excess value and when it's by a row of pads it's a different excess value. Some designers would then use the courtyard excess as a test point (no-probe) keep-out (which can be done in the new V2016.07 pre-release available here - http://www.pcblibraries.com/downloads" rel="nofollow - www.pcblibraries.com/downloads .

Some say that the Courtyard Excess should be based on the package Height with a minimum/maximum limit and we are looking into that also. Example is a BGA that needs lights and camera inserted somewhere on the edge of a BGA to inspect solder joints for cracks.

However, it's difficult to build every little detail about PCB layout into a library part. The PCB designer has to have some knowledge of Design for Fabrication and Assembly and don't place tall parts close to short parts because reworking the short parts becomes impossible without damaging the tall part.

i.e.: the PCB designer most have knowledge of all the manufacturing and rework processes to Design for Excellence.

We are currently experimenting with a new SMD Proportional Pad Stack mathematical model that produces the solder joint goals (Toe, Heel and Side) from the package height or gull wing lead thickness. The height is also used to auto-generate the courtyard excess.

We will keep you up to date with our progress.

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Posted By: Todd Manning
Date Posted: 16 Jun 2016 at 3:57pm

Hi Tom,

Thanks for the detailed response. I look forward to see how this progresses in the future.

Regards
Todd

Posted By: Tom H
Date Posted: 23 Jul 2016 at 7:52am

With the microminiaturization of the component package industry and updated manufacturing equipment we are proposing these new Courtyard Excess values:

0.10 - Least
0.20 - Nominal
0.40 - Maximum

Library Expert V2016.08 introduced 40 new Terminal Lead Preference options so the Gull Wing leads are now broken up by component family and by pin pitch. Rectangular End Cap (Chips) are broken up by size.

Download the new Excel Spreadsheets to se the new IPC-7351C proposed solder joint goals and updated courtyard excess here - http://www.pcblibraries.com/downloads" rel="nofollow - www.pcblibraries.com/downloads and select "IPC-7351 Solder Joint Goal Tables"

We also recommend that you talk to your assembly shop to insure they are using the latest placement equipment. If not, ask them what the nominal space between component packages with average package Height od 1.60 mm should be for their manufacturing process.

Always leave at least 0.40 mm (twice the normal amount) between packages that are over 10.00 mm Height. These are Connectors and Aluminum Electrolytic Capacitors.

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Posted By: Todd Manning
Date Posted: 04 Aug 2016 at 7:21pm

Thanks for the updated information.

Todd

Posted By: Tom H
Date Posted: 05 Aug 2016 at 7:00am

There is a Preference file called PCB Libraries.dat that contains all the proposed new solder joint goals for IPC-7351C.

Also, the latest release is V2016.09, however there is a V2016.10 pre-release that has these new features and fixes - http://www.pcblibraries.com/downloads" rel="nofollow - www.pcblibraries.com/downloads

· Calculator:

o Updated the indicator light in the Viewer to enhance the description of the various colors

o Fixed all parts with Thermal Tabs with disappearing radius corners when outputting Terminals

· FP Designer:

o Fixed the pin text so long pin names will not overlap

· 3D STEP:

o Fixed Side Concave 2, 4-Pin Oscillator for micro-miniature version

· Expedition:

o Fixed a problem that was causing the layers not to fully display

o Fixed a problem that was preventing the Component Outline from being translated into a Placement Outline

· Allegro:

o The 17.2 pad stack scripts will now set the unit precision manually to 4 decimal places. This mirrors what was done previously and allows it to not rely on the default precision.

· CR-5000:

o m callouts for solder mask pads will split out properly to be used for the pad name when using IPC-7351 naming

o Adjusted the naming so that the corners callout stays with its copper pad name, and not the paste mask callout of the pad name

o Fixed a bug that was causing paste mask checkerboard to also be generated outside of the pad stack, causing an error

· OrCAD Layout:

o Terminal Shapes will be redirected to Layer 16 (Comment Layer)

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Posted By: Todd Manning
Date Posted: 07 Aug 2016 at 4:07pm

When do you find out if the proposed new solder joint goals are accepted or not?

Posted By: Tom H
Date Posted: 07 Aug 2016 at 4:35pm

The IPC-7351 mathematical model which includes the component package, terminal lead, placement and fabrication tolerances have not changed at all.

Only the Toe, Heel and Side values have been updated to include 40 new incremental pin pitches. These new values are in-line with IPC-J-STD-001 for solder joint goal acceptability.

i.e.: One Gull Wing solder joint goal does not work for all DPAK's, SOP's, QFP's, SOT's and SOD's. There are differences in each component family and each pin pitch range.

IPC-7351C is scheduled for release around September 2017.

It's up to you the end user to discuss the solder joint goals and the IPC-7351 mathematical model with your Assembly Shop. The new values are simply a starting point for discussion and anyone can voice their proof that they work or fail. They're just suggestions for a baseline and IPC-7351C has been downgraded from a "Standard" to a "Guideline".

Here are the V2016.10 pre-release notes so far - http://www.pcblibraries.com/downloads" rel="nofollow - www.pcblibraries.com/downloads

· Calculator:

o Updated the indicator light in the Viewer to enhance the description of the various colors

o Fixed all parts with Thermal Tabs with disappearing radius corners when outputting Terminals

· FP Designer:

o Fixed the pin text so long pin names will not overlap

· 3D STEP:

o Fixed Side Concave 2, 4-Pin Oscillator for micro-miniature version

· PADS to CAD:

o Fixed an issue that was causing the corner radius on rounded rectangles to only be half what they should be when importing PADS files

· PADS:

o Fixed an issue that was causing D-Shaped pads to translate to PADS improperly

· Expedition:

o Fixed a problem that was causing the layers not to fully display

o Fixed a problem that was preventing the Component Outline from being translated into a Placement Outline

· Allegro:

o The 17.2 pad stack scripts will now set the unit precision manually to 4 decimal places. This mirrors what was done previously and allows it to not rely on the default precision.

· CR-5000:

o m callouts for solder mask pads will split out properly to be used for the pad name when using IPC-7351 naming

o Adjusted the naming so that the corners callout stays with its copper pad name, and not the paste mask callout of the pad name

o Fixed a bug that was causing paste mask checkerboard to also be generated outside of the pad stack, causing an error

· OrCAD Layout:

o Terminal Shapes will be redirected to Layer 16 (Comment Layer)

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Posted By: mspittel
Date Posted: 02 Sep 2016 at 2:44pm

Not sure of IPC Standard implications but it would be nice to decouple the courtyard and manufacturing excess from the copper/mask patterns. I have found it very useful to use LMC criteria for creating copper/mask patterns but then open the courtyard to MMC conditions. Satisfies the CM wishes and desire by mgt to keep costs low for assembly....

It can be done thru maual settings but would be convenient to have as clearly identifiable option.... Maybe an option within defaults....