PCB Libraries Forum : Features & Training

Features & Training : PCB Pad & Footprint Orientation

Thu, 18 Sep 2025 00:40:00 +0000

Author: dramos
Subject: PCB Pad & Footprint Orientation
Posted: 18 Sep 2025 at 12:40am

Dear Tom and Team,

Many thanks for your comments. They give me many ideas to conduct the meeting in the desired way.

After reading the FED-18 document, I could imagine that there could be the problem you described. Something similar happened to me with Tantalum caps. In my opinion, the most interesting thing is to read how other people deal with similar problems you had. To see the same problem from another perspective. But any way, it is an interesting document.

"A CAD Librarian would have to know what a good nominal dimension is and a reasonable tolerance." For that purpose we should learn more and more about pcb fabrication and assembly. This is what makes our job so challenging, always you find something new to learn, a new concept or idea for fooprints, a new assembly technics,...

Thanks again for your interesting comments.

Regards,

david

Features & Training : PCB Pad & Footprint Orientation

Tue, 16 Sep 2025 16:08:41 +0000

Author: Tom H
Subject: PCB Pad & Footprint Orientation
Posted: 16 Sep 2025 at 4:08pm

When I tried to convince Dieter Bergman to change the zero component orientation back to the original rotation, Dieter just shrugged his shoulders and said "Let the best standard win". Once a standard is published it takes years to undo anything.

Jami Smith had a compelling explanation (he sounded like a salesman) and Karen wanted to give the attendees an opportunity to vote on the subject. She forgot that 90% of the people in the conference meeting at APEX were not on the 1-13 committee. People just walked in to find out what was going on and they got a chance to vote on a very important issue. In hindsight, I could have swayed the vote by simply mentioning IPC-SM-782 but I didn't and the industry suffered a major bad decision.

The FED Proportional Pad Stack feature was recently added to Footprint Expert, but we ran into a problem with calculating pad stack using percentages of package dimensions. Example: The 0805 chip component family has a dozen different heights and to calculate the Toe uses 40% of the package height. This would create 12 different footprints for the same Case Code.

So we used the IPC J-STD-001 to calculate an acceptable Toe for a 0805 chip component. We then took every component family and every terminal lead and created Toe, Heel and Side goals that would be acceptable to meet J-STD-001 assembly. You can use Footprint Expert Nominal Calculation Mode but you need knowledge of solder joint goals. We did a good job at creating the default solder joint goal values, but they are intended to be adjusted by the end user.

When you download hundreds of thousands of component datasheets and compare the manufacturer recommended pattern to the Nominal Calculation Mode, you realize the manufacturers do not use Min/Max calculations. They use Nominal Package Dimensions and apply a Toe, Heel and Side (just like the FED Volume 18 concept). Component manufactures don't use the tolerances they publish in their datasheets for their recommended pad stack pattern.

The IPC-7352 uses Min/Max Calculation Mode which is dependent on the mfr. package tolerances to form the solder joint goals. The major flaw in the Min/Max technology is that component manufacturer tolerances are too robust or not truly accurate and sometimes just composed and unrealistic. The CAD Librarian must be familiar with package tolerances and spot bad tolerance data in the mfr. datasheets.

Example: for years SOIC manufacturers had an 'L' tolerance of 0.41 mm X 1.27 mm. This tolerance is way too robust and not realistic for today's machine technology. This tolerance makes the pad length way too big. A CAD Librarian would have to know what a good nominal dimension is and a reasonable tolerance. Same concept applies to every component family and terminal lead in the electronics industry. Use reasonable tolerances.

BTW: it looks as though component manufacturers are finally realizing that their package and terminal tolerances impact the pad stack calculation and they are reducing their tolerances to be closer to reality. It took us long enough to get the component manufacturers to use standard package dimension characters and standard component family name references. It was out of control 20 years ago.

All the best to the CAD librarians around the world who have to make these decisions everyday. I wish all of you good luck in making the best informed choices for your CAD library.

Features & Training : PCB Pad & Footprint Orientation

Tue, 16 Sep 2025 15:02:24 +0000

Author: dramos
Subject: PCB Pad & Footprint Orientation
Posted: 16 Sep 2025 at 3:02pm

Hi,

Many thanks for the explanation, for letting know us why IPC-7351C never existed. I remember that we waited for long for the new "C" version and at the end it was named IPC-7352 and it was downgraded to a "guideline".

Do you think the IPC will recover in the future the "spirit" of the IPC-SM-782 about pin1 orientation? Perhaps so many time doing the things without knowing "why" in that way, that someone will want to standardize it with any reason...

After reading your grate explanation about what happened, I have a question about it: Why Ms. K.McConnell accepted the explanation of Mr. J.Smith?

Thanks to PCBFE I read a very interesting article from Mr. Rainer Taube about "New Proportional Land Dimmension" and after that I read the full article in FED-18, do you think this new concept will be more visible in a close future?

Could it replace the maths of IPC-7352 and the solder joints concepts?

Many thanks again for sharing your experiences and knowledge.

Best regards,

david

Features & Training : PCB Pad & Footprint Orientation

Thu, 11 Sep 2025 09:20:34 +0000

Author: Tom H
Subject: PCB Pad & Footprint Orientation
Posted: 11 Sep 2025 at 9:20am

You need to know why IPC-7351 zero component orientation came into existence.

I joined the 1-13 IPC Land Pattern Committee in 1999 to help Dieter Bergman with a IPC-SM-782 software calculator to replace the IPC on-line land pattern calculator that was very expensive for IPC to maintain.

My first goal was in 2000 to transition from using imperial units to designing PCB library parts and PCB layout using the metric measurement system. The first calculator Jeff and I created was an Excel spreadsheet with called LandCalc. It was primarily SMD and only supported metric units. This was to run all tests to ensure the IPC mathematical model for min/max calculations was perfect.

The first calculators only had one rotation 'Pin 1 Lower Left' which was what the IPC-SM-782 supported since March 1987. After all, it was just an Excel spreadsheet and we didn't have the luxury of multiple rotations.

It took 2 years to add all the component families and finalize the min/max mathematical model. Then thanks to Philip Restall in the UK, we added a CAD tool translator for Mentor Graphics PADS. PADS was ASCII format so it was easy to figure out and we renamed the Excel spreadsheet to LandWiz. We freely distributed LandWiz on a website www.pcbstandards.com and had lots of downloads.

Then in 2003 we started writing code for the first software program which was Land Pattern Wizard. We shortened the name to LP Wizard. It was unique because there was only one footprint rotation 'Pin 1 Lower Left' because user feedback wanted us to fully dimension the resulting footprint to make it easy to QC.

Then IEC introduced the 3-Teir PCB library solution and we had to change everything to add the Least, Nominal and Most solder joint goals. This took another year to implement into the software tool.

We completed LP Wizard in 2004 with 3-Teirs, lower left was the zero component orientation and metric units only. We delivered it to IPC to test and replace their on-line calculator.

IPC was interested in getting volunteers involved in the approval process and were signing up volunteers quickly. We invited industry experts in join the IPC committee. Unfortunately, many of the volunteers turned out to be takers rather than givers. They attended meetings get information rather than provide information.

IPC had the final 1-13 Land Pattern Committee meeting at the 2004 IPC APEX conference in Anaheim, CA. We invited everyone in the local area to attend, especially members of local IPC Designer Council members. I spoke at the local San Diego chapter meetings regarding this new technology and try to convince everyone to transition to the metric measurement system. One attendee at the meeting was Jami Smith. He liked to attend IPC Designer Council meetings to learn more about standards in the electronics industry. Jami said he was interested in helping with the new land pattern committee, but the committee had already completed their goal of upgrading IPC-SM-782 to IPC-7351. But there was one more meeting at IPC APEX in Anaheim, CA and Jami Smith attended the meeting. He was about 30 minutes late getting to the meeting and when he entered, he recognized me and sat next to me. I was running the projector through my lap top showing the committee the new LP Wizard software program and the IPC-7351 draft.

80% of the attendees at his final meeting were newbies who never attended a single Land Pattern meeting. They were just people who wanted to learn more about the new standard. Also, this was the first and last IPC Land Pattern Committee meeting that Jami Smith attended. We were all set to finalize the standard when Jami stood up to address the attendees. He claimed to have knowledge of EIA-481 and insisted that the EIA zero component orientation for pick and place machines was Pin 1 'Upper Left'. No one at the APEX meeting knew anything about EIA-481 so they took Jami's word that he was trying to contribute information that we were unaware of.

Vern Solberg was one of the committee leaders and he suggested a committee vote from everyone in the room. Don't forget that 80% of the attendees had never attended a standards meeting before and they were asked to vote on an important subject. Karen McConnell the committee chairman was there and she agreed with Jami Smith. Then when everyone voted, they sided with Karen and Jami and that was the turning point for the IPC-7351 Zero Component Orientation. Jami Smith left the meeting and no one ever saw him again. But the damage was done.

It took us 3 - 4 months to change all the footprint rotations in LP Wizard. IPC-7351 was released in 2005. IEC got involved and chastised IPC for changing the footprint rotation based on faulty information and a rash decision at a meeting that no one had the knowledge of what impact they had on the entire electronics industry. So IEC released the IEC 61188-7 which reverted back to IPC-SM-782 zero component orientation.

Dieter Bergman and I had a conversation in 2008 about changing the zero component orientation for IPC-7351B, but Dieter said that once a standard is released it's very difficult to say you were wrong and here's the correction. Dieter shrugged his shoulders and said "Let the best standard win". However, in 2014 the IEC standard was winning and Dieter agreed to change the zero component orientation in the new IPC-7351C. We had the kick-off meeting at IPC headquarters the week of July 15 - 19. We created the entire framework for the new totally upgraded IPC-7351 standard. I left the meeting and flew back to San Diego, CA and immediately started working that weekend on Chapters 5 for surface mount and 6 for through-hole. The following week on July 23, Dieter Bergman passed away. This was a devasting loss to the electronics industry but I was inspired to carry the torch and spent the next year writing the IPC-7351C with Rainer Taube in Germany. We introduced IPC-7351C to the Land Pattern Committee in 2016 and we worked on refining it for 6 years. Then we found out that Dieter never had the approval by the IPC executive committee for IPC-7351C and they shelved it, never to be released.

Bottom line is that the Pin 1 in the upper left for xero component orientation should have never been released and Jami Smith will go down in history for changing a standard that he had no business being involved in. Jami disappeared never to be heard from or seen again.

And now you know - the rest of the story...

Features & Training : PCB Pad & Footprint Orientation

Thu, 11 Sep 2025 07:04:39 +0000

Author: dramos
Subject: PCB Pad & Footprint Orientation
Posted: 11 Sep 2025 at 7:04am

Dear Nick and Team,

In our company, there is a great discussion about the pin1 orientation. To use IPC-7351 or to use IEC-61188-7.

I've read the article of the Top, and at the end my conclusions are:

- IEC-61188-7, is and standard very extended in Europe and some countries in ASIA that over the years has been consistent, has not changed. In other hand IPC-7351 modified the criteria from IPC-SM-781.

In the article is mentioned that it was an error, could you tell me an example? I have not the experience of PCBFE.

- IEC-61188-7, is more close to the IEC-481 from the point of view of the pin1 on reel.

- JEDEC has pin1 in cuadrant 1.

Is there anything else that I missed that I could argue to convince to my colleagues to use IEC-61188-7?

That's true that PCBFE gives us the possibility to configure it, but we would like to use the same .opt file on each site of the company.

Thanks for your comments.

david

Features & Training : Logical Descriptions in Footprint Expert

Mon, 07 Apr 2025 03:13:15 +0000

Author: Nick B
Subject: Logical Descriptions in Footprint Expert
Posted: 07 Apr 2025 at 3:13am

Logical Descriptions are mostly used by the EE engineer in the schematic symbol. The Logical Description defines the electronic function of the device and is not usually imported into a PCB Footprint. The PCB designer is mostly interested in the Physical Description as it defines the physical attributes of the component package that solders to the PCB.

The Logical Description is usually in the schematic Bill of Materials (BOM) and that becomes part of the PCB designer's documentation for the CAD library which ties the schematic symbol with the PCB footprint. Logical Descriptions come from several places and there is no standard format that defines them. To achieve the highest level of automation, everything should be standardized. Even the Logical Description.

Organize the Logical Description by component family. Examples: IC, Transistor, Inductor, Capacitor, Connector, Header, Resistor, Crystal.

Semiconductor datasheets usually provide the Logical Description on the first page of the component datasheet. Texas Instruments primarily produces semiconductors, and their datasheets are meta data friendly to allow you to copy/paste the Logical Description. Put 'IC' before the description.

It is important to note that most library PLM systems are ASCII data and "symbols" are not ASCII. Do not copy/paste symbols from a PDF datasheet into your PLM library. Symbols include:

Here are sample semiconductor datasheets.

Note: if the Logical Descriptions contain the word 'with', exclude everything after that to keep the Logical Description less than 80 characters.

Texas Instruments:

IC, USB Type-C DRP Port Controller

Linear Technology:

IC, Low IQ, Dual 2 Phase Synchronous Step-Down Controller

Analog Devices:

IC, Bidirectional, Wide Positive and Negative Sensing Range

Discrete components are much more complex than semiconductors because a single datasheet represents multiple devices with different values.

Note: the rule for spaces in the Logical Description

Single capital letters like V, W, A have no space between the value and the letter.

Multiple capital letters like VWM, MHz, GHz have a space between the value and the letters.

Multiple letters that start with a capital letter like ‘Ohm' have a space between the value and the letters.

Multiple letters that start with a lower-case letter like uH, mOhm, uF, nH have no space between the value and the letters.

Note: the rule for commas in the Logical Description. A space always follows the comma:

Component Family,
Package,
Type,
Value,

The component family always is first, followed by the package style and function and last the values.

Resistor: Resistor, Chip, Thick Film, 196K Ohm, 1%, 1/8W

Capacitor 1: Capacitor, Chip, Multilayer Ceramic, 2.2uF, 10%, 10V, X7R

Capacitor 2: Capacitor, Molded, Tantalum Polymer, 22uF, 10%, 50V, X7R

Inductor: Inductor, Low Profile, IHLP Power, 150nH, 26A, 2.5mOhm

Diode: Diode, TVS, 350 VWM, 564 VC, 64A

Transistor: Transistor, Bipolar NPN, 40V, 200mA, 300 MHz, 625mW

Crystal: Crystal, Mobile Communications, 38.4 MHz

Connector Logical Descriptions can be organized by these parameters.

Type: Connector, Header, Terminal Block
Number of Positions: 24 Position
Pin Pitch: 0.50 mm Pitch
Function: D-Sub, RJ45, HDMI, USB Type 2, Board-to-Board, FFC, BNC, Audio, Backplane
Number of Rows: Single Row, Dual Row
Sex: Male or Plug, Female or Receptacle or Socket
Rotation: Right Angle or Vertical

Example: Connector, 140 Position, 0.80 mm Pitch, Board-to-Board, Dual Row, Receptacle, Vertical

PCB Footprint Expert

The Footprint Expert, in conjunction with the online part database, allows you to maintain quality Logical Description data! The Footprint Expert helps you create flawless PCB designs much more efficiently!

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Features & Training : PCBL Case Codes

Sun, 30 Mar 2025 16:57:40 +0000

Author: Nick B
Subject: PCBL Case Codes
Posted: 30 Mar 2025 at 4:57pm

Component manufacturer Case Codes (Package ID's) are in the datasheet on the package dimension page. Every manufacturer has a unique case code for their specific package dimensions. If a Case Code does not exist for non-standard packages, the Part Number is used as a substitute. Sometimes discrete components will have a standard JEDEC or EIA Case Code for SODs, SOTs, Chips and Molded Body packages, but using the JEDEC and EIA Case Code name is misleading as every component manufacturer has slightly different dimensions than the JEDEC specifications. However, when a component manufacturer is acquisitioned by another manufacturer, the Case Codes could be changed.

Sometimes the manufacturer Part Number includes the Case Code.

Sample JEDEC Case Codes:

TO-253 – SOT143
TO-261 – SOT223
TO-276 – DFN3
TO-252 – DPAK
DO-213 – MELF
DO-214 – Molded Body Diodes, SMA, SMB, SMC
DO-218 – SOD
DO-221 - SODFL

Sample EIA Case Codes:

SOT23 – Transistor
0201, 0402, 0603, 0805, 1206 – Chip
6032, 7343 – Molded Body
SOD123, SOD323, SOD523, SOD723 – Diode

All electronic devices today have unique Part Numbers but sometimes share the same Case Code. All connector Part Numbers are the Case Code, as all connector solder patterns are unique.

Some component manufacturers provide good Case Codes. Here are examples of manufacturers that provide good Case Codes.

NXP Semiconductor Case Codes start with SOD or SOT followed by a number. NXP refers to their Case Codes as 'Outline Version' and it's placed in the upper right corner of the component package dimensions page in the data sheet. Nexperia is a spinoff of NXP and they use the same SOD/SOT prefixes for their Case Codes.

Here is the component package datasheet page with the Case Code SOT917-1 in the Upper Right.

Texas Instruments Case Codes were originally JEDEC descriptors.

Example: D R-PDSO-G14

D = TI identifier, R = Rectangle, PDSO = Plastic Dual Small Outline, G = Gullwing with 14 leads

When Texas Instruments acquired National Semiconductor, management preferred the NS Case Codes, so they are in the process of replacing all the JEDEC Case Codes with National Semiconductors.

The original TI Case Code D R-PDSO-G14 was recently changed to D0014A. The D0014A Case Code is assigned to over 5,000 TI Part Numbers. Over the past 10 years, TI updated Case Codes for over 100,000 Part Numbers. If you're into creating large PCB library databases, you're constantly updating Part Numbers with new Case Codes.

Here is a footprint and 3D model for TI Code D0014A.

Here is the component datasheet page with the Case Code in the Upper Left and package dimensions.

Analog Devices Case Codes start with 05-08-XXXX, but they also use Case Codes from their acquisition of Linear Technologies that begin with CP followed by a hyphen – and a number. Example: CP-10-9

Analog Devices also acquisitioned Maxim Integrated and took over their Case Codes that start with 21- followed by a 4-character numeric code 21-XXXX.

Diodes, Inc. Case Codes include a variety of JEDEC, EIA and Component Family abbreviations like DFN, QFN, SOP, SOT, DPAK, SOD and DIP. However, be aware that Diodes, Inc. uses the same Case Code, but the packages have various dimensions like SOT23. This is because Diodes acquired ZETEX and their SOT23 used different package dimensions but still uses the same Case Code. The SOT23 Case Code can be spelled in different ways, and each version has different package dimensions. Examples: SOT23, SOT-23, SOT-23-3, SOT23 DN, SOT23F and SOT23R.

On Semiconductor changed its name to onsemi. The Case Codes for onsemi start with the word "CASE" followed by a space and a sequence of alphanumeric characters. Example: CASE 318BA = SOT-23. Onsemi acquisitioned Fairchild Semiconductor which uses JEDEC and component family abbreviations but most of their Case Codes start with the letter M and followed be a string of alphanumeric characters. Example: MA03D = SOT-23.

Infineon Technologies uses various techniques for Case Code names. JEDEC – PG-TO-2522-3, IR followed by numbers, P-TQFP-100-3, PG-DSO- (pin qty), PG- Component Family abbreviation (LGA, SOP, QFP, etc.). Infineon acquisitioned Cypress Semiconductor and added their Case Codes that start with 001- and 51- followed by 5 numeric characters. Example: 001-04468 = QFN and 51-85064 = QFP.

Microchip Technology uses component family abbreviations and the pin quantity for their Case Codes. Examples: 8-SOIC, 64-QFN, 128-QFP, etc. They also use the prefix C04- followed by 3 numeric characters and the letter to represent the revision. Microchip acquisitioned Microsemi and incorporated their Case Codes that have a prefix of CASE followed by a letter. Microchip also acquisitioned Atmel and incorporated their Case Codes which begin with a number that represents the pin quantity followed by a random letter. Example: 86T = 86-pin SOP

Cirrus Logic uses the component pin quantity + package abbreviation. Examples: 32L QFP, 44L PLCC, 48L QFN, 14L SOIC, 10L DFN.

FTDI Chip uses the package abbreviation + pin quantity. Examples: QFP48, QFN32, VQFN48, WQFN28, SOP20, TSSOP20, SSOP20.

Renesas Electronics uses L + pin quantity + overall package dimensions + version letter. Examples: L10 3x3B, L12 3x3D, L16 4x4A, L8 2x2C. They also use an M + pin quantity + .XX + version letter. Examples: M14.173A, M16.15A, M10.118, M28.209. Integrated Device Technology was acquired by Renesas, and they used a P + the Lead Shape G = Gullwing, J + J-Lead, L = PLCC + the package abbreviation. Examples: PG24 = SOP24, PJ28 = SOJ28, PL68 = PLCC68.

Silicon Labs uses package abbreviation + pin quantity. Examples: DFN6, LGA42, QFP100, MSOP10, SOIC8, QFN20. They also use Si as a prefix followed by a random number. Examples: Si53306, SI32261, SI5338B, Si5395J.

Wurth Elektronik uses a 9-character code for their part numbers, and the part number is also used as the Case Code. Examples: 749022011, 750313995, 750032052, etc.

All the chip manufacturers use EIA Case Codes like 0201, 0402, 0603, 0805, 1206, etc. These manufacturers include AVX, Vishay, Yageo, Panasonic, KEMET, ROHM, KOA, Stackpole, Susumu, Ohmite.

All connector manufacturers have unique part numbers and no Case Codes, so the Part Number is used as the Case Code. The connector footprint names are MfrNameAbreviation_MfrPartNumber.

Non-standard Discrete and Semiconductor packages footprint names are always MfrNameAbreviation_CaseCode.

The main issue is that component manufacturers should do a better job at creating unique Case Codes that represent their package dimensions. The package code should be located on the component dimensions page of every datasheet, and it should be obvious to every CAD librarian, PCB designer and EE engineer. The Case Code should be added to every schematic symbol and appear in every Bill of Material (BOM).

Component manufacturers need to be aware that all PCB design layouts require solder patterns for every component package that they produce. Errors are created when manufacturers do not provide Case Code package IDs for all their package dimensions.

The upside for assigning Case Codes (package IDs) for every component is that a CAD librarian only needs to spend time creating the Case Code solder pattern and then the EE engineer could assign a Part Number with the correct Case Code.

Let's use Texas Instruments as an example for this concept. TI has 3,000 Case Codes and each one requires a unique solder pattern. This is what the PCB designer requires for the PCB layout. However, TI produces over 250,000 electronic device part numbers that map to the 3,000 Case Codes and that is a responsibility for the EE engineer. The PCB designer provides the Case Code to the EE engineer and the engineer assigns a part number with the correct manufacturer Case Code in the BOM. This will greatly enhance the productivity of the PCB designer and reduce errors, costs and turnaround time. Case Codes are a very important aspect of every electronic product.

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Features & Training : PCB Pad & Footprint Orientation

Mon, 17 Feb 2025 16:50:00 +0000

Author: Tom H
Subject: PCB Pad & Footprint Orientation
Posted: 17 Feb 2025 at 4:50pm

In PADS Layout, the Bottom (Opposite) Side footprint rotation is clockwise.

The Top Side footprints rotate counterclockwise.

It could be different for each CAD tool.

Features & Training : What's Wrong with Your Footprint?!

Thu, 30 Jan 2025 12:13:02 +0000

Author: Nick B
Subject: What's Wrong with Your Footprint?!
Posted: 30 Jan 2025 at 12:13pm

The free Footprint Calculator and the Footprint Expert are compared here:

https://www.pcblibraries.com/products/compare

To download and use the free Footprint Calculator:

1. Login at https://www.PCBLibraries.com/downloads
(login with existing account, or register for free)

2. If you see this button, click it:

3. If you do not see it, you already have a Key. Click this button to download:

4. Install and run the Calculator, then use your Email and Key (full key displayed on Download page) to activate the Calculator license.

PCB Footprint Expert

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Features & Training : Free Footprint Calculator or Footprint Expert?

Thu, 30 Jan 2025 12:12:42 +0000

Author: Nick B
Subject: Free Footprint Calculator or Footprint Expert?
Posted: 30 Jan 2025 at 12:12pm

The details below are just some of the differences (yes, there are more!) between the Footprint Expert footprints and the libraries available all over the internet. Most don’t realize how lacking all those footprints online really are, but they can be much worse than lacking when they actually cost you money.

Footprint Expert	Source 1	Source 2

AUTO-GENERATED library parts use predefined or user-modified rules – share across your organization; RULES-based, auto-generated part library	MANUALLY CREATED by many different people, using countless rules – results in a board with inconsistently built parts, far more prone to introduction of costly errors; massive variations in parts inconducive to standardized rule-based library
Built to exact datasheet specification, either Metric or Mils	Units vary based on source, and Metric often converted from Mils with rounded-off measurements; converting pin pitch often results in leads not fully centered on pads
User-defined consistency of line widths for all parts	Many different line widths used across different footprints due to lack of standard rules
Accurate contour courtyards are auto generated	Sloppy or non-existing contour courtyards
Relevant data: Footprint Name, Physical and Logical Descriptions, datasheet link, and more	Nothing, or inconsistent random data
Auto-generated keep outs on all non-plated holes for copper poly shapes, traces and vias	Missing keep-out will cause DRC errors at the manufacturer if copper, traces, and vias are placed within 0.25 mm of the non-plated hole
Pin 1 polarity markers for silkscreen and assembly	Pin 1 markings missing or vary in shape and in size
Footprint Origin at center of gravity	Footprint Origins randomly placed
Uniform, silkscreen outlines are whole objects mapped to the maximum package dimensions	Silkscreen is fragmented and mapped to the nominal package dimensions
Clear, consistent, intelligently placed markings to minimizes use of board space	Inconsistent and extra markings and excessive courtyards requires more placement space
Consistent silkscreen trimming around all pads	Inconsistent and random silkscreen trimming around pads
Solder Mask swell auto-applied and configurable	Inconsistent solder mask swell from one footprint to another
Through-hole pad stack hole sizes automatically defined by maximum terminal lead diameter, and pad size auto-calculated by 1.5 x hole diameter	Lack of published, consistent rules to define through-hole pad stacks make it impossible for proper quality control of resulting footprint, results in capriciously calculated footprints
Non-plated holes have smaller pad sizes to prevent copper slivers after drilling process	Non-plated holes have a pad size equal to the hole size create risk of copper slivers after the drilling process; the plane antipad is randomly defined with no obvious rules

The Footprint Expert automates footprints to perfection. Professional, detailed, and accurate parts – all built consistently with identical rules, regardless of how many people are involved in your library development.

Get your FREE Footprint Calculator or Footprint Expert Evaluation License:
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