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  <title>PCB Libraries Forum : TXS02612RTWR Footprint Issues</title>
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  <description><![CDATA[This is an XML content feed of; PCB Libraries Forum : Footprints / Land Patterns : TXS02612RTWR Footprint Issues]]></description>
  <pubDate>Wed, 15 Apr 2026 02:19:59 +0000</pubDate>
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   <title><![CDATA[TXS02612RTWR Footprint Issues : The TI footprint that you originally...]]></title>
   <link>https://www.PCBLibraries.com/forum/txs02612rtwr-footprint-issues_topic2244_post9287.html#9287</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2244<br /><strong>Posted:</strong> 31 Oct 2017 at 6:14am<br /><br />The TI footprint that you originally downloaded was created in FP Designer. <br /><br />If the part is created in the Calculator then anyone can apply their preferences for Solder Mask swell, Pad Shape, Paste Mask Reduction and use the mfr. recommended pattern. <br /><br />You can also move the footprint from the Calculator to FP Designer to add the via matrix for the Thermal Pad. <br /><br />Keeping the part in the Calculator will produce a better 3D STEP model. <br /><br />]]>
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   <pubDate>Tue, 31 Oct 2017 06:14:04 +0000</pubDate>
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   <title><![CDATA[TXS02612RTWR Footprint Issues : Now I was able to export in Altium...]]></title>
   <link>https://www.PCBLibraries.com/forum/txs02612rtwr-footprint-issues_topic2244_post9286.html#9286</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=12428">toshas</a><br /><strong>Subject:</strong> 2244<br /><strong>Posted:</strong> 31 Oct 2017 at 4:13am<br /><br /><p>Now I was able to export in Altium without any issues.<br>Thanks!</p><p>I'm working on prototype board and new footprint will be ok for it.</p><p>But other users may prefer old footprint (which was made exactly per datasheet recomendations: with thermal via and so on).</p><p>Is it possible to keep both ones in PCB Library ? Without direct replacement ?</p><p>Thanks again!</p>]]>
   </description>
   <pubDate>Tue, 31 Oct 2017 04:13:09 +0000</pubDate>
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   <title><![CDATA[TXS02612RTWR Footprint Issues :  Thanks a lot! ]]></title>
   <link>https://www.PCBLibraries.com/forum/txs02612rtwr-footprint-issues_topic2244_post9285.html#9285</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=12428">toshas</a><br /><strong>Subject:</strong> 2244<br /><strong>Posted:</strong> 30 Oct 2017 at 10:13pm<br /><br />Thanks a lot!]]>
   </description>
   <pubDate>Mon, 30 Oct 2017 22:13:30 +0000</pubDate>
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   <title><![CDATA[TXS02612RTWR Footprint Issues : We updated the Texas Instruments...]]></title>
   <link>https://www.PCBLibraries.com/forum/txs02612rtwr-footprint-issues_topic2244_post9284.html#9284</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2244<br /><strong>Posted:</strong> 30 Oct 2017 at 1:52pm<br /><br />We updated the Texas Instruments part on POD to allow you to use your default pad shape in Preferences. <br /><br />The part was converted from FP Designer to the Calculator for a better 3D STEP model.<br /> ]]>
   </description>
   <pubDate>Mon, 30 Oct 2017 13:52:30 +0000</pubDate>
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   <title><![CDATA[TXS02612RTWR Footprint Issues : There are duplicate Pin Names...]]></title>
   <link>https://www.PCBLibraries.com/forum/txs02612rtwr-footprint-issues_topic2244_post9283.html#9283</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2244<br /><strong>Posted:</strong> 30 Oct 2017 at 12:42pm<br /><br />There are duplicate Pin Names for the Thermal Pad Vias. <br /><br />Altium can handle multiple pins with the same pin name. <br /><br />If not, delete the via pad stack and resave the part. <br />]]>
   </description>
   <pubDate>Mon, 30 Oct 2017 12:42:16 +0000</pubDate>
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   <title><![CDATA[TXS02612RTWR Footprint Issues :  2-3 solved!Actually Altium does...]]></title>
   <link>https://www.PCBLibraries.com/forum/txs02612rtwr-footprint-issues_topic2244_post9282.html#9282</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=12428">toshas</a><br /><strong>Subject:</strong> 2244<br /><strong>Posted:</strong> 30 Oct 2017 at 12:38pm<br /><br />2-3 solved!<div>&nbsp;</div><div>Actually Altium does not support D-Shape pads. After replacement D-Shape to Oblong 2-3 are gone.</div>]]>
   </description>
   <pubDate>Mon, 30 Oct 2017 12:38:04 +0000</pubDate>
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   <title><![CDATA[TXS02612RTWR Footprint Issues :  Hi!I downloaded TXS02612RTWR...]]></title>
   <link>https://www.PCBLibraries.com/forum/txs02612rtwr-footprint-issues_topic2244_post9281.html#9281</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=12428">toshas</a><br /><strong>Subject:</strong> 2244<br /><strong>Posted:</strong> 30 Oct 2017 at 10:45am<br /><br />Hi!<div>&nbsp;</div><div>I downloaded TXS02612RTWR footprint and have some issues with it:</div><div><ol><li>"Dublicate pin name 25 exists in...." message during CAD export wizard in Library Expert.</li><li>Short circuit violation on every pin in Altium&nbsp;during DRC check. "&#091;Short-Circuit Constraint Violation&#093;&nbsp;PCB.PcbDoc&nbsp;Advanced PCB&nbsp;Short-Circuit Constraint: Between Region (0 hole(s)) Top Layer And Pad IC?-10 (52.25 mm, 43.025 mm)&nbsp; Top Layer Location : &#091;X = 1121.95mm&#093;&#091;Y = 648.925 mm&#093;"</li><li>Unable to apply "solder mask/paste expansion" rules to pads when footprint placed on PCB.</li></ol></div><div>&nbsp;</div><div>What is wrong with this part ?</div><div>&nbsp;</div><div>Thanks a lot!</div><div>&nbsp;</div>]]>
   </description>
   <pubDate>Mon, 30 Oct 2017 10:45:27 +0000</pubDate>
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