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  <title>PCB Libraries Forum : JEDEC Standard Footprints?</title>
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  <pubDate>Wed, 15 Apr 2026 07:14:06 +0000</pubDate>
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   <title><![CDATA[JEDEC Standard Footprints? : You need separate Chip land patterns...]]></title>
   <link>https://www.PCBLibraries.com/forum/jedec-standard-footprints_topic2063_post8490.html#8490</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2063<br /><strong>Posted:</strong> 23 Jan 2017 at 12:46pm<br /><br />You need separate Chip land patterns for Capacitors and Resistors. <div><br></div><div>Capacitors should have a side fillet and Resistors do not. </div><div><br></div><div>However, IPC says that the same pattern can be used for both because the Side Fillet is not required per IPC-J-STD-001. </div><div><br></div><div>They do mention in Note 3 that there should be "Visible Wetting" but that's not possible with chips that do not have a terminal lead wraparound. </div><div><br></div><div><img src="uploads/3/J-STD-001_Chip.png" height="390" width="964" border="0" /></div><div><br></div><div><br></div><div>Here are 3D models created by Library Expert Pro. </div><div><br></div><div><img src="uploads/3/0603_Chips.png" height="423" width="662" border="0" /><br></div>]]>
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   <pubDate>Mon, 23 Jan 2017 12:46:11 +0000</pubDate>
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   <title><![CDATA[JEDEC Standard Footprints? : JEDEC pacjkage are onhttp://ww...]]></title>
   <link>https://www.PCBLibraries.com/forum/jedec-standard-footprints_topic2063_post8489.html#8489</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=2519">Louis_Guerin</a><br /><strong>Subject:</strong> 2063<br /><strong>Posted:</strong> 23 Jan 2017 at 12:21pm<br /><br />JEDEC pacjkage are on&nbsp;<a href="http://www.jedec.org/category/technology-focus-area/jc-10/registered-outlines-jep95&nbsp;" target="_blank" rel="nofollow">http://www.jedec.org/category/technology-focus-area/jc-10/registered-outlines-jep95&nbsp;</a><div><br></div><div>As Tom mentionned you have to register to have them.</div><div><br></div><div>As for the RC0402 I've though of it once, however PCB patterns cap are a bit wider than resistors because of sides that can be soldered which is not the case for resistors and in some case this extra surface could cause placement problem on crowded PCB.&nbsp;</div><div>Of course you can use the resistor pattern for both of them but then why cap have component end covered on all side and not the resistor?</div><div>Could somebody enlight us on this?&nbsp;<img src="https://www.PCBLibraries.com/forum/smileys/smiley25.gif" border="0" alt="Questi&#111;n" title="Questi&#111;n" /></div>]]>
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   <pubDate>Mon, 23 Jan 2017 12:21:56 +0000</pubDate>
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   <title><![CDATA[JEDEC Standard Footprints? : When you download the JEDEC datasheets...]]></title>
   <link>https://www.PCBLibraries.com/forum/jedec-standard-footprints_topic2063_post8488.html#8488</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2063<br /><strong>Posted:</strong> 23 Jan 2017 at 12:18pm<br /><br /><div>When you download the JEDEC datasheets and look at the package dimensions, try to match them with your mfr.'s package dimensions. </div><div><br></div><div>You will find out that they are close but not a direct match. </div><div><br></div><div>I think that mfr.'s need to pay JEDEC a royalty if they use their package dimensions. Therefore they change them slightly. </div><div><br></div><div>But I agree with you in that one SOIC8 footprint should be good for all, but only if the package dimensions are within a 0.20 mm tolerance of each other. </div><div><br></div>]]>
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   <pubDate>Mon, 23 Jan 2017 12:18:45 +0000</pubDate>
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   <title><![CDATA[JEDEC Standard Footprints? : Thanks for the JEDEC info ......]]></title>
   <link>https://www.PCBLibraries.com/forum/jedec-standard-footprints_topic2063_post8487.html#8487</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=12085">craig4tone</a><br /><strong>Subject:</strong> 2063<br /><strong>Posted:</strong> 23 Jan 2017 at 12:14pm<br /><br /><div>Thanks for the JEDEC info ... I just assumed is was pay-to-play like IEEE papers.</div><div><br></div>Can you please clarify what you mean by "very few mfr.'s use these"?<div><br></div><div>The parts are created at an IC packaging facility of which several manufacturer's share the same facilities and SOT, SOIC, TSSOP, etc. are all built to JEDEC standards because of existing tooling that was created back when SMT adopted the standards. &nbsp;Granted, the newer, unique packages such as the PDSON-8, thermal pad devices, etc. are the exception to that rule, but I am referring to the "industry standard" parts like 0402 resistors, SOT23-3, SOT23-5, SOIC8, SOIC8W, SMA, SMB, SMC, EIA molded body, etc.</div>]]>
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   <pubDate>Mon, 23 Jan 2017 12:14:37 +0000</pubDate>
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   <title><![CDATA[JEDEC Standard Footprints? : For the standard JEDEC package...]]></title>
   <link>https://www.PCBLibraries.com/forum/jedec-standard-footprints_topic2063_post8486.html#8486</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2063<br /><strong>Posted:</strong> 23 Jan 2017 at 12:03pm<br /><br /><div>For the standard JEDEC package dimensions - <a href="http://www.jedec.org/%20" target="_blank" rel="nofollow">http://www.jedec.org/ </a></div><div><br></div><div>However, very few mfr.'s use these. </div><div><br></div><div>SOIC = MO-059, -099, -119, -120</div><div>SOP40 = MO-154</div><div>SOP65 = MO-150</div><div><br></div><div>Just register on JEDEC.org and download all MS, MO, DO and TO PDF files. </div><div><br></div><div><br></div><div><br></div>]]>
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   <pubDate>Mon, 23 Jan 2017 12:03:00 +0000</pubDate>
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   <title><![CDATA[JEDEC Standard Footprints? : To precursor the discussion, I...]]></title>
   <link>https://www.PCBLibraries.com/forum/jedec-standard-footprints_topic2063_post8485.html#8485</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=12085">craig4tone</a><br /><strong>Subject:</strong> 2063<br /><strong>Posted:</strong> 23 Jan 2017 at 11:53am<br /><br />To precursor the discussion, I have been involved in PCB and ECAD Management for 25+ years. &nbsp;I have worked exclusively as a Manager for Library Services company in the past and have seen it all both good and bad.<div><br></div><div>I am now working for a service-based company and we purchased Library Expert in order to maintain a centralized component database that we can export to various toolflows and with various settings (IPC-7351C vs. customer-specific, etc.)</div><div><br></div><div>In my experience, there is little merit in creating 20 variations of an SOIC-8 (3.9mm width) per manufacturer. &nbsp;This only serves to make the library confusing as well as create potential problems with PCB re-use in the case of obsolescence. &nbsp; I.e. TI disco's a PN and On Semi has a replacement but the "recommended pads" or tolerancing creates a wider IPC-7351C pattern that creates a DRC if replaced and the PCB MUST remain the same for compliance reasons (UL, FCC, etc.). &nbsp;I also have "friends" that work for un-named chip vendors and the "recommended footprints" and package drawings are most often a joke as the datasheets are created by interns and that info is often copy/pasted from unknown sources and/or Google. &nbsp;<img src="https://www.PCBLibraries.com/forum/smileys/smiley36.gif" border="0" alt="LOL" title="LOL" /></div><div><br></div><div>With that being said, where can I find JEDEC package mechanical drawings to build parametric libraries from? &nbsp;</div><div><br></div><div>I am thinking of standardizing things such as SOT, SOIC, chip components, molded body caps, SM* diodes, etc. &nbsp;What if any standardization of footprints have any of you attempted? &nbsp;I'm even toying with the idea of combining resistor and cap 0402 into a single "RC0402" package with a worst case ceramic cap height.</div>]]>
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   <pubDate>Mon, 23 Jan 2017 11:53:08 +0000</pubDate>
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