<?xml version="1.0" encoding="utf-8" ?>
<?xml-stylesheet type="text/xsl" href="RSS_xslt_style.asp" version="1.0" ?>
<rss version="2.0" xmlns:WebWizForums="https://syndication.webwiz.net/rss_namespace/">
 <channel>
  <title>PCB Libraries Forum : Via Naming Convention</title>
  <link>https://www.PCBLibraries.com/forum/</link>
  <description><![CDATA[This is an XML content feed of; PCB Libraries Forum : OrCAD Layout : Via Naming Convention]]></description>
  <pubDate>Wed, 15 Apr 2026 07:12:23 +0000</pubDate>
  <lastBuildDate>Tue, 13 Dec 2016 14:40:02 +0000</lastBuildDate>
  <docs>http://blogs.law.harvard.edu/tech/rss</docs>
  <generator>Web Wiz Forums 12.07</generator>
  <ttl>360</ttl>
  <WebWizForums:feedURL>https://www.PCBLibraries.com/forum/RSS_post_feed.asp?TID=2038</WebWizForums:feedURL>
  <image>
   <title><![CDATA[PCB Libraries Forum]]></title>
   <url>https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif</url>
   <link>https://www.PCBLibraries.com/forum/</link>
  </image>
  <item>
   <title><![CDATA[Via Naming Convention : Where is a via naming convention...]]></title>
   <link>https://www.PCBLibraries.com/forum/via-naming-convention_topic2038_post8355.html#8355</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=3">Tom H</a><br /><strong>Subject:</strong> 2038<br /><strong>Posted:</strong> 13 Dec 2016 at 2:40pm<br /><br /><div>Where is a via naming convention at?</div><div><br></div><div>The anti-pad is for both Positive and Negative planes and it represents a very important value in the pad stack, especially for vias. </div><div><br></div><div>If the anti-pad diameter should not be larger than the pad annular ring + trace space. </div><div><br></div><div>You do not want to run high speed signal traces over a plane&nbsp;anti-pad. The plane is the signal return path and&nbsp;trace couples with the plane. </div><div><br></div><div>In the via pad stack, you have to define the pad, hole, anti-pad and direct plane connect (flood over) for a normal copper pour plane flood. </div><div><br></div>]]>
   </description>
   <pubDate>Tue, 13 Dec 2016 14:40:02 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/via-naming-convention_topic2038_post8355.html#8355</guid>
  </item> 
  <item>
   <title><![CDATA[Via Naming Convention : Isn&amp;#039;t it time to drop the...]]></title>
   <link>https://www.PCBLibraries.com/forum/via-naming-convention_topic2038_post8354.html#8354</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://www.PCBLibraries.com/forum/member_profile.asp?PF=9507">bnoel</a><br /><strong>Subject:</strong> 2038<br /><strong>Posted:</strong> 13 Dec 2016 at 2:05pm<br /><br />Isn't it time to drop the zz from the following via naming conventinon: &nbsp;via-xx-yy-zz &nbsp;where xx is the pad diameter, yy is the hole diameter and zz is the anti-pad diameter? &nbsp;We haven't been using negative planes in years and I believe most EDA tools have gotten away from them too. &nbsp;Thoughts.]]>
   </description>
   <pubDate>Tue, 13 Dec 2016 14:05:40 +0000</pubDate>
   <guid isPermaLink="true">https://www.PCBLibraries.com/forum/via-naming-convention_topic2038_post8354.html#8354</guid>
  </item> 
 </channel>
</rss>