PCB Libraries Forum : Densly packing tall components https://www.PCBLibraries.com/forum/ Wed, 15 Apr 2026 05:42:42 +0000 Wed, 26 Feb 2014 07:16:12 +0000 http://blogs.law.harvard.edu/tech/rss Web Wiz Forums 12.07 360 https://www.PCBLibraries.com/forum/RSS_post_feed.asp?TID=1266 <![CDATA[PCB Libraries Forum]]> https://www.PCBLibraries.com/forum/forum_images/PCBLForumLogo.gif https://www.PCBLibraries.com/forum/ <![CDATA[Densly packing tall components : I&#039;m getting the FP Designer...]]> https://www.PCBLibraries.com/forum/densly-packing-tall-components_topic1266_post4988.html#4988 Author: Tom H
Subject: 1266
Posted: 26 Feb 2014 at 7:16am

I'm getting the FP Designer and the Library Expert Calculator mixed up here.

The IPC Calculator is just a recommendation (not a hard coded standard).

Placement Courtyard sizes for each 3-Tier Environment are -

  1. Least = 5 mil (0.12 mm)
  2. Nominal = 10 mil (0.25 mm)
  3. Most = 20 mil (0.50 mm)

The User can change the courtyard excess value to anything you want in User Preferences or on the fly in the IPC Calculator.


]]> Wed, 26 Feb 2014 07:16:12 +0000 https://www.PCBLibraries.com/forum/densly-packing-tall-components_topic1266_post4988.html#4988 <![CDATA[Densly packing tall components : The FP Designer is Strictly used...]]> https://www.PCBLibraries.com/forum/densly-packing-tall-components_topic1266_post4987.html#4987 Author: Tom H
Subject: 1266
Posted: 26 Feb 2014 at 7:11am

The FP Designer is Strictly used for Mfr. Recommended Footprint patterns for Non-Standard component packages that do not fit into the IPC Calculator.

The user defines the placement courtyard size based on their personal requirements (because the component manufacturer's do not recommend any courtyard dimensional data).

 

]]> Wed, 26 Feb 2014 07:11:25 +0000 https://www.PCBLibraries.com/forum/densly-packing-tall-components_topic1266_post4987.html#4987 <![CDATA[Densly packing tall components : In my present commission I am...]]> https://www.PCBLibraries.com/forum/densly-packing-tall-components_topic1266_post4985.html#4985 Author: NeilVP
Subject: 1266
Posted: 26 Feb 2014 at 3:57am

In my present commission I am required to mount 80+ CAPC6050x500 capacitors into a relatively small area. In experimenting with FP Expert I noticed that the courtyard does not vary with the height of the component and my concern is that placing a lot of tall components, courtyard to courtyard, may cause problems in reflow as there may be problems with shadowing in IR ovens and dead spots if using forced air convection.
My questions are - is my concern realistic and are there any further recommendations for this situation? 
 
Many thanks
 
Neil
]]> Wed, 26 Feb 2014 03:57:10 +0000 https://www.PCBLibraries.com/forum/densly-packing-tall-components_topic1266_post4985.html#4985